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| pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use pm3351 elan 1x100 single port fast ethernet switch data sheet issue 3: february 1998
pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use i contents features............................................................................................................ 1 block diagram ................................................................................................. 3 description ...................................................................................................... 4 introduction .................................................................................................... 5 switch processor ........................................................................................... 5 multi-channel dma processor........................................................................ 6 ethernet/ieee 802.3 mac interface .............................................................. 6 expansion port............................................................................................... 6 local memory controller ................................................................................ 7 clocking and test .......................................................................................... 7 typical system application........................................................................ 8 low-cost 10/100 mbit/s switching hub .......................................................... 8 primary features and benefits ...............................................................9 wire-speed frame switching........................................................................... 9 combined input- and output-buffered switch ................................................ 9 modular design. ............................................................................................. 9 advanced switching features ......................................................................... 9 spanning tree bridging capabilities .............................................................. 10 management and monitoring support .......................................................... 10 autoconfiguration via local prom/eeprom.............................................. 10 pin diagram ..................................................................................................... 12 208-pin quad flat pack pin diagram .......................................................... 12 pin description ............................................................................................. 13 functional grouping..................................................................................... 15 pci expansion bus interface ....................................................................... 16 mii interface pins ......................................................................................... 17 local memory interface ............................................................................... 18 clock inputs and outputs............................................................................. 19 miscellanous inputs and outputs................................................................. 20 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use ii dc characteristics ..................................................................................... 21 absolute maximum ratings ......................................................................... 21 recommended operating conditions.......................................................... 21 d.c. characteristics ..................................................................................... 22 ac characteristics ..................................................................................... 23 pci bus interface......................................................................................... 24 mii interface ................................................................................................. 25 memory interface ......................................................................................... 27 15 ns sram ac timing ......................................................................... 27 150 ns eeprom/eprom ac timing .................................................... 28 60 ns edo dram ac timing................................................................. 29 clocking ....................................................................................................... 31 miscellaneous .............................................................................................. 31 functional description............................................................................. 32 overview ...................................................................................................... 32 system components.................................................................................... 32 system block diagram ........................................................................... 33 system memory map.............................................................................. 34 device internal blocks ................................................................................. 37 switch processor .................................................................................... 37 100mbit/s ethernet mac interface ......................................................... 38 multichannel dma controller ....................................................................... 43 memory controller ....................................................................................... 46 pci expansion port...................................................................................... 47 watchdog timer facility ......................................................................... 51 device configuration .............................................................................. 52 system bootstrap image ........................................................................ 54 configuration parameters....................................................................... 60 self test and error reporting................................................................. 61 data structures ............................................................................................ 63 switch processor operating environment .............................................. 64 packet buffers ........................................................................................ 68 data descriptors..................................................................................... 71 transfer rings ........................................................................................ 74 local port descriptor and port descriptor counters...............................76 expansion port descriptor table ............................................................ 84 address hash table ............................................................................... 86 free pools .............................................................................................. 94 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use iii spanning tree support data structures................................................. 96 rtos requirements .............................................................................. 97 udp/ip protocol stack requirements .................................................... 97 snmp requirements .............................................................................. 97 storage requirements............................................................................ 97 switching system initialization ................................................................... 100 frame switching process .......................................................................... 101 address learning and aging...................................................................... 115 local address learning........................................................................ 116 remote learning process .................................................................... 117 default hash bucket............................................................................. 118 buffer and queue management................................................................. 122 buffer management .............................................................................. 123 transmit fifo management ................................................................124 broadcast rate limiting ....................................................................... 125 statistics collection.................................................................................... 126 messaging protocol ................................................................................... 128 spanning tree operation........................................................................... 129 rtos operation ........................................................................................ 129 udp/ip protocol stack operation .............................................................. 129 snmp operation........................................................................................ 129 device interface via pci ............................................................................ 129 frame transfer to non-elan devices ................................................. 129 participation in address learning ......................................................... 129 participation in the messaging protocol................................................ 129 accessing variables and statistics ....................................................... 129 byte ordering ....................................................................................... 129 default byte ordering ........................................................................... 130 alternate byte ordering ........................................................................ 131 elan 1x100 / elan 8x10 expansion bus data transfer rates ..........131 pci register/memory access ................................................................. 137 pci configuration space ........................................................................... 137 pci configuration registers ................................................................. 138 pci memory space.................................................................................... 147 local memory access........................................................................... 148 device control/status registers........................................................... 148 device configuration registers ............................................................ 150 device debug registers ....................................................................... 155 request and acknowledge counter registers ..................................... 155 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use iv programmer's model................................................................................ 157 local memory ............................................................................................ 158 register map.............................................................................................. 158 general-purpose registers .................................................................. 158 special-purpose registers ................................................................... 158 control registers .................................................................................. 159 register descriptions ................................................................................. 163 cpu special registers ......................................................................... 163 device control registers ...................................................................... 164 rpcim functional block (pci access dma channel) ................................ 173 debug functional block........................................................................... 182 dpi functional block (dma transmit channel) ........................................... 187 tx_fifo functional block: ................................................................................. 191 major components of the tx_fifo datapath ....................................... 191 tx_fifo interrupts to switch processor .............................................. 192 disposition of frames:.......................................................................... 192 dpo funtional block (dma transfer handshake channel)........................... 199 hash functional block ............................................................................... 215 interrupts to swtich processor ................................................................... 226 gpi (switch processor general purpose inputs)....................................... 230 gpo (switch processor general purpose outputs) .................................. 231 coprocessor test conditions..................................................................... 235 operation...................................................................................................... 237 power supply sequencing ......................................................................... 237 mechanical information ......................................................................... 238 ordering and thermal information ................................................... 240 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 1 features single-chip, 1-port, full duplex or half duplex, 10/100baset switching device for low-cost unmanaged and managed networks. on-chip 50 mhz risc cpu processor core, multi-channel dma controller, mac-layer interface logic, fifos, pci-based expansion port and a flexible memory controller. cpu supports background applications running on local os (e.g., snmp or rmon), and real-time data oriented applications (e.g., frame forwarding and filtering decisions). performs frame switching at a rate of 200 mbit/s (full duplex), 100 mbit/s (half duplex). fully compatible with the pm3350, 8-port 10 mbit/s switch device; may be used to create a compact and inexpensive mixed 10/100 mbit/s switching hub. store-and-forward operation with full error checking and filtering. filtering and switching at wire rates (up to 148,800 packets per second), supporting a mix of ethernet and ieee 802.3 protocols. expansion port supports a peak system bandwidth of 1 gbit/s, and is compatible with industry-standard pci bus (version 2.1). performs all address learning, address table management and aging functions for up to 32,768 mac addresses (limited by external memory). address learning rate of up to 100,000 addresses per second. maximum broadcast/multicast at wire rates with configurable broadcast storm rate limiting. low-latency operation in both unicast and broadcast modes. implements the link partition function to isolate malfunctioning segments or hosts. ieee 802.1d compliant spanning-tree transparent bridging supported on-chip, with configurable aging time and frame lifetime control. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 2 flow control supported for both full duplex and half duplex operation: supports ieee 802.3x pause frame flow control in full-duplex mode, and supports user- enabled backpressure flow control in half-duplex mode with configurable buffer thresholds and limits. configuration, management, mib statistics and diagnostics available in-band or out-of-band. maintains and collects per-port and per-host statistics at wire rates, allowing a network switch comprised of pm3351 and pm3350 chips to implement rmon statistics (etherstats and hoststats) using supplied on-chip firmware. interfaces directly to industry-standard 100 mbit/s transceivers with no glue logic via the built-in medium independent interface (mii) port with full support for the autonegotiation function implemented by the phy devices. fully static cmos operation at 50 mhz clock rates. 3.3 volt core, 5 volt compatible i/o 208 pin pqfp package. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 3 block diagram external memory interface transmit channel logic 50 mhz embedded cpu i cache pci bus interface pci expansion bus sram / eprom expansion registers 100baset mii i/f tx fifo 100baset transmit mac rx fifo 100baset transmit mac receive dma controller d cache pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 4 description the pm3351 is a low-cost, highly integrated stand-alone single-chip switching device for 10/100 mbit/s ethernet (ieee 802.3u, ieee 802.12) switching and bridging applications. the device supports all processing required for switching ethernet packets between the on-chip medium independent interface (mii) port and the built-in 1 gbit/s expansion port, to which other pm3351 (elan 1x100) or pm3350 (elan 8x10) devices may be attached. the pm3351 is directly compatible with the pm3350, 8-port 10mbit/s ethernet switch chip. the pm3351 can be used with the pm3350 to create non-blocking switches of the configurations shown in the table below, with each 100 mbit/s port configured for full- duplex and each 10 mbit/s port configured for half-duplex switch configuration # pm3350 chips # pm3351 chips 4 x 100 mbit/s 0 4 3 x 100 mbit/s + 16 x 10mbit/s 2 3 2 x 100 mbit/s + 40 x 10 mbit/s 5 2 1 x 100 mbit/s + 56 x 10 mbit/s 7 1 0 x 100 mbit/s + 64 x 10 mbit/s 8 0 a switch built using the pm3351 can be expanded to use up to 7 additional devices on the pci expansion bus; the limitation to 8 devices is a result of using dedicated internal counters for implementing the elan switch protocol over the expansion bus. for details on the expected expansion bus data traffic requirements for different combinations of pm3350 and pm3351 chips please refer to section expansion bus data transfer rates . all of the initialization, switching, interfacing, management and statistics gathering functions are performed by the pm3351, minimizing the size and cost of a switching hub with one or more 100 mbit/s ports. switch configuration and management can be performed either remotely (in-band), via the on-chip snmp mib, agent and integrated tcp/udp/ip stack, or from a local cpu interfaced to the expansion port. the elan 1x100 also collects per-port and per-host pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 5 rmon statistics at wire rates on all ports. the pm3351 chip contains all the required elements of a high-performance ethernet switch: an mii interface for connection to physical-layer transceivers, mac-layer processing logic, buffer fifos, a high-speed dma engine for fast frame transfers, a local memory interface for up to 4 mbytes of external buffer memory, a compatible pci bus master and slave unit for modular expansion, and a switch processing unit that implements the switching and bridging functions. the only additional components required for each 100 mbit/s switch port are an mii compliant transceiver (supports 100basetx/fx, 100baset4,100baset2, and any future 802.3-compliant 100mbit mii phys), passive line interface devices, a bank of external memory and a system clock. the amount of external memory may range up to 4 mbytes, depending on the amount of frame buffering required and the number of mac addresses to be supported, and may be implemented using standard asynchronous sram devices with 15 nsec access times. switch configuration information is provided to the pm3351 using a single eprom or eeprom; only one eprom is required in a multiple pm3351/pm3350 system. the elan 1x100 device is implemented in a high-density, low-voltage cmos technology for low cost and high performance. it is available in a 208-pin quad flat pack, and is ideally suited for compact, low-cost desktop, workgroup and departmental ethernet switching applications. device data introduction the elan 1x100 (pm3351) offers a complete system-level solution, integrating all required elements (except frame/address memory and transceiver logic) in a single high-density vlsi chip. it is a true single-chip switch; all the required functions, including management, rmon-level statistics collection, spanning tree support and self-configuration, are performed by the elan 1x100 without need for external cpus or logic. in addition, the functions required for expandability are also integrated into the device. the elan 1x100 is built around a risc cpu based switching processor core which is closely coupled with a multi-channel dma controller, mac-layer interface logic, fifos, a pci-based expansion port and a flexible memory controller. switch processor an on-chip switch processor is primarily responsible for performing the ethernet / ieee 802.3 frame routing functions, and can switch packets arriving simultaneously from the single100baset port and the expansion port at full wire rates using address tables that it creates and maintains in external local memory. store-and-forward switching is pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 6 performed, allowing the switch processor to detect crc, length and alignment errors and reject bad packets. the switch processor also supports ieee 802.3 group/functional address handling. address aging, topology change updates, and statistics collection are performed by the switch processor as well. the switch processor unit allows the device to support high-level capabilities. it implements the full ieee 802.1d spanning-tree transparent bridging protocol, which allows the elan 1x100 to act as an expandable learning bridge, performing learning, filtering and redirection at full speed. rmon statistics collection, plus a messaging system to support master/slave communications in a multi-device switch, are also implemented by the switch processor. when additional switch devices are connected to the elan 1x100 expansion port, the switch processors in all pm3350 and pm3351 elan chips intercommunicate to transfer frames to each other and also transparently support a distributed snmp/rmon mib. multi-channel dma processor the on-chip dma controller contains four independent and concurrently operating channels: one for receiving frames over the 100baset port; another for transmitting frames over the same port; and two that are dedicated to the expansion port. the dma controller operates under the control of the switch processor to transfer packets and data at high speed between the 100baset port, the local memory and the expansion port. it also computes 32-bit ieee frame check sequence (fcs) crc remainders over the transferred packets, allowing the switch processor to filter packets with errors and generate crcs for transmitted packets as required. control logic is provided to support full and half-duplex operation, as well as the handling of management traffic. ethernet/ieee 802.3 mac interface one ethernet/ieee 802.3u mac-layer interface based on the media independent interface (mii) is built into the elan 1x100 chip. it connects directly to the external 100baset compatible phy devices via the industry-standard mii interface, and performs all of the mac-layer processing tasks required for csma/cd networks. both full-duplex and half-duplex modes of operation are supported at 10 and 100 mbit/s data rates. the mac interface includes independent receive and transmit fifo buffers to support sustained full wire rate operation. configuration and initialization of the attached 100mbit/s phy devices can be performed using the mii management interface. this is accomplished by using the mii pins mdio and mdclk to read, write and poll the management registers built into an mii-compliant phy device. this allows the pm3351 to support auto-negotiation, link status, and other management operations on the attached phy device(s), including the next page functions. serial management functions are implemented by the switch processor for maximum flexibility and "standards-proofing". pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 7 expansion port a 32-bit parity-checked pci-based expansion port is provided to allow the elan 1x100 to communicate transparently with other pci bus devices to implement switches that have multiple 100mbit/s and 10mbit/s ports. the expansion port supports a maximum throughput of over 1 gbit/s, and requires only a single pal or similar device serving as a bus arbiter. a common protocol is used for inter-chip communication between the elan 1x100 (pm3351) and elan 8x10 (pm3350). packets received on an elan 1x100 mac port that are destined for an external elan switch chip are transferred over the expansion bus prior to transmission on the designated destination port. broadcast and multicast packets are handled using a two-level replication scheme, in which the broadcast/multicast frame is first transferred to all of the external elan switch chips, after which it is transmitted out the required destination ports without any further use of the expansion bus. (in the case of an elan 1x100, only one port is present in each destination device, and hence only one level of replication takes place.) in addition, elan switch chips interconnected via the pci bus exchange information to maintain the distributed mib. the expansion port is compatible with the industry-standard peripheral component interconnect (pci) specification version 2.1, which allows the elan 1x100 chip to be directly interfaced to any host computer supporting the pci bus. the host cpu can then communicate with the elan 1x100 and control its functions, greatly expanding the range of potential applications. the maximum pci clock of 40 mhz is supported. local memory controller the local memory is used for holding configuration information, mac address tables and statistics tables, node management data, packet buffers, and host communication queues if a local host cpu is present. the elan 1x100 integrates a memory controller that is capable of addressing and directly driving up to 16 mbytes of external memory, divided into four banks of 4 mbytes each, with decoded selects for each bank. 1 independent, software programmable access times may be set for each bank, allowing a glueless interface to a mix of sram, , eeprom, and eprom in the same system. an external memory timing generator may also be used if desired. the memory controller accepts simultaneous requests from the switch processor, the dma processor, and the expansion port, and efficiently partitions the 100 mbyte-per-second memory port bandwidth among them. the elan 1x100 is capable of auto-configuring after power-up via an 8-bit eprom or eeprom connected to the memory port. parameters (such as the mac address, ip 1 when accessing sram and eeprom devices, however, the actual limit is 1 mbyte per bank, as the upper bits of the internal address bus are not brought out to physical pins. the entire 4 mbytes per bank is only accessible when using dram memory types. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 8 address, configuration options, etc.) may be placed in this eprom or eeprom, and will be loaded automatically by the elan 1x100. 1 clocking and test the pm3351 is implemented in fully-static cmos technology, and can operate at any device clock frequency between 45 and 50 mhz (25 to 40 mhz for the expansion port bus). the switch processor performs a comprehensive power on self test (post), and can report failure conditions and device status in a variety of ways (an 8-bit led interface register connected to local memory, writing to a host over the pci bus, writing to a serial port interface connected to local memory, etc). 1 the elan 1x100 follows the same configuration process as the elan 8x10 chip. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 9 typical system application low-cost 10/100 mbit/s switching hub the pm3351 chip can act as a high-speed server or backbone port in low-cost, compact ethernet switching hub applications. such a hub can be created from one or more pm3351 devices (one for every 100 mbit/s port required), 1 to 7 pm3350 chips (one for every eight 10 mbit/s ports required), a bank of memory per device (60 nsec dram for each pm3350, 15 ns sram for each pm3351) for holding frame buffers and switching tables, a single 32k x 8-bit eeprom device for configuration information, two lxt944 10baset interface adapters per pm3350 chip, one lxt 970 100 mbit/s phy device per pm3351, and suitable passive components (filters, transformers, crystal oscillators, etc.). a block diagram of a typical 32-port 10baset stackable switching hub with two 100 mbit/s server/backbone ports is given in the following diagram. the stacking connectors allow multiple switch assemblies to be seamlessly stacked. expandable 10/100 mbit/s ethernet switch elan 8x10 8x10baset pm3350 pci backplane 8 x 10baset 10/100baset 8 x 10baset quad phy edo dram elan 8x10 8 x 10baset pm3350 quad phy elan 8x10 8x10baset pm3350 elan 1x100 1x10/100 baset pm3351 quad phy quad phy 10/100 phy edo dram sram elan 8x10 8x10baset pm3350 edo dram edo dram eepro m elan 1x100 1x10/100 baset pm3351 sram quad phy quad phy quad phy quad phy 10/100baset 10/100 phy 8 x 10baset 8 x 10baset pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 10 primary features and benefits as an ethernet switching/bridging solution, the pm3351 offers a number of benefits in a low-cost switching hub: wire-speed frame switching. each pm3351 chip performs all of the functions required to implement a 10/100 mbit/s full/half duplex switch port at wire rates (ranging from 148,808 frames/sec for a frame size of 64 bytes to 8130 frames/sec for a frame size of 1518 bytes). no additional logic, microprocessors, etc. are necessary. in addition, the low cost and compact size permitted by the single-chip pm3351 solution permits high-speed server or backbone ports to be added to even entry-level switching hubs very simply. combined input- and output-buffered switch the elan 1x100 implements a hybrid input-buffered/output-queued switching algorithm which minimizes the possibility of frame loss, allows buffers to be allocated on a demand basis, and permits limits to be established to prevent any one memory consumer from acquiring all system buffer memory. frame buffer storage is allocated within the external memory by the elan 1x100 from a central pool using an on-demand method, employing linked lists of small, fixed-length buffers to hold variable sized packets in order to maximize memory utilization. modular design. multiple pm3351 chips interconnect with no external glue logic (beyond a simple pci arbiter device), allowing a family of scalable switches to be built without redesign. when used in conjunction with the pm3350 single-chip 8-port 10 mbit/s ethernet switch, a 10/100 mbit/s switching hub can be realized at low cost. the 1 gbit/s expansion port bandwidth ensures that network capacity grows linearly as more chips from the elan switch family are added. advanced switching features the elan 1x100 implements per-frame lifetime control to ensure that transmit queues are flushed properly in the event of bottlenecks at the output ports. address aging is handled on-chip, as is purging of the address table in the event of a network reconfiguration. broadcast storm rate limiting is implemented (with configurable rate limits) to reduce the effects of high broadcast rates on the traffic flowing through the switch. two different methods of flow control are supported: backpressure for a half- duplex link and 802.3x pause mac control frames for a full-duplex link. flow control is a user-selectable feature, with the thresholds and limits capable of being user- configured in order to minimize frame loss in heavily loaded networks. backpressure is pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 11 performed by jamming (colliding with) incoming packets on the 100mb port when the port has no free receive buffers. spanning tree bridging capabilities the elan 1x100 is capable of supporting the 802.1d spanning tree protocol, allowing it to interoperate with ieee-standard transparent bridges. the spanning tree protocol is supported by the on-chip switch processor unit, and does not require an external cpu for implementation, as the actual agent may be supported on the switch processor on one of the pm3350 chips. management and monitoring support the elan 1x100 (pm3351) maintains and collects rmon port and host statistics for all learned mac addresses at wire rates. these statistics may be retrieved either in-band (via snmp agent) or out-of-band (via the expansion bus). when multiple elan 1x100 and elan 8x10 chips are present in a system, they may be configured to intercommunicate and create a distributed mib in a transparent manner. 1 status codes may be displayed on a set of leds (light emitting diodes) during self-test and operation at the system implementer's discretion. these status codes are output to a register mapped into the elan 1x100 memory data bus at a specific address location. device failure during self-test, or specific operating conditions, may be displayed using front-panel leds connected to the register. an optional on-chip watchdog timer is provided by the erst* output of the elan 1x100. the erst* output of the device can be tied directly to the rst* input to provide an optional system-wide watchdog reset. this facility permits the elan 1x100 to force an automatic system restart whenever a fatal error is encountered during operation. autoconfiguration via local prom/eeprom the elan 1x100 automatically self-configures upon power-up using user-defined parameters supplied in an external eprom or eeprom. the eprom/eeprom may be connected to the memory bus and mapped to any address range; the elan 1x100 will automatically locate the eprom or eeprom and load the configuration parameters from it. the elan 1x100 also contains hardware that enables it to write to standard 3.3-volt eeprom devices, thus permitting configuration information to be changed dynamically. 1 the elan 8x10, if present in the system, can directly implement an optional on-chip snmp agent on top of an integral tcp/udp/ip protocol stack, supporting snmp and the rfc1493 bridge mib, and supplying snmp access to the statistics gathered by the elan 1x100 (as well as the other devices in the system). alternatively, the system vendor may elect to disable the snmp agent and access all chip statistics and configuration variables directly from the expansion port. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 12 in a system with multiple elan devices, the master device (whether elan 1x100 or elan 8x10) can load its configuration information and then configure the other elan devices over the expansion bus, allowing configuration of the entire system with one eprom. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 13 pin diagram the pm3351 is packaged in a 208-pin pqfp, with 135 signal pins, 36 vss (gnd) pins, 31 vdd (3.3v) pins, and two 5v supply pins. the vss and vdd pins are split between internal (core) & i/o buffer pins (8 vssi, 8 vddi, 28 vsso, & 23 vddo pins). all pins must be connected properly. attention should be given to the 4 no-connect pins. 208-pin quad flat pack pin diagram devsel* bias5 vsso ad31 ad30 ad29 ad28 vddo vsso ad27 ad26 ad25 ad24 cbe3 vddo vsso frame* idsel trdy* irdy* vddo vsso ad23 ad22 ad21 ad20 ad19 ad18 vsso vddo vssi vddi ad17 gnt* cbe2 vsso req* int* vddo vsso ad15 ad14 ad13 ad12 ad11 cbe1 vsso vddo ad10 ad9 ad8 ad16 1 10 20 30 40 50 70 80 90 100 110 120 130 140 150 208 160 170 180 190 200 60 vsso vddo rx_clk tx_clk vddo vsso ad7 ad6 vddi vssi ad5 ad4 ad3 vsso vsso ad1 ad0 vddo vsso vddo clk25 sysclk stop* perr* serr* par rst* pciclk vddo ad2 cbe0 memclk nc mdio vddo vsso vssi vddi mdc erst* vsso vddo rxd3 rxd2 rxd1 rxd0 rx_dv rx_er tx_en txd0 bias5 vsso maddr10 maddr11 maddr12 maddr13 maddr14 maddr15 maddr16 maddr17 vddo vsso mcs0* mcs1* mcs2* mcs3* maddr1 maddr2 maddr3 vddo vssi vsso maddr4 maddr5 maddr6 maddr7 maddr8 maddr9 vsso vsso vddo vssi vddi txd1 txd2 txd3 col crs vsso vddo vddi maddr0 mrdy* mrd* mwr3 mwr2 vsso vddo mwr1 mwr0 mgwe mras* vsso vddo mdata10 mdata11 vssi vddi mdata13 mdata14 mdata15 mdata16 mdata17 mdata18 mdata20 mdata21 mdata22 mdata23 mdata24 mdata25 mdata26 mdata27 mdata28 mdata29 mdata30 mdata31 vddi vssi nc tst* mintr* mdata0 mdata3 vddo vsso mdata2 mdata4 vsso mdata5 mdata6 mdata7 mdata8 mdata12 mdata9 vsso mdata19 vsso vddi vssi vsso vddo vddo vddo mdata1 nc nc elan 1x100 pm3351 208 pqfp pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 14 pin description pin signal pin signal pin signal pin signal 1 bias5v 53 vddo 105 vddi 157 vddi 2 vsso 54 vsso 106 vssi 158 vssi 3 ad31 55 stop * 107 txd1 159 mdata31 4 ad30 56 perr * 108 txd2 160 mdata30 5 ad29 57 serr * 109 txd3 161 mdata29 6 ad28 58 par 110 col 162 mdata28 7 vddo 59 rst * 111 crs 163 vsso 8 vsso 60 pciclk 112 vsso 164 mdata27 9 ad27 61 vddo 113 vddo 165 mdata26 10 ad26 62 vsso 114 maddr17 166 mdata25 11 ad25 63 ad7 115 maddr16 167 mdata24 12 ad24 64 ad6 116 maddr15 168 vsso 13 cbe3 65 vddi 117 maddr14 169 vddo 14 vddo 66 vssi 118 vsso 170 mdata23 15 vsso 67 ad5 119 maddr13 171 mdata22 16 frame * 68 ad4 120 maddr12 172 mdata21 17 devsel * 69 ad3 121 maddr11 173 mdata20 18 idsel 70 ad2 122 maddr10 174 mdata19 19 trdy * 71 vddo 123 vsso 175 mdata18 20 irdy * 72 vsso 124 vddo 176 mdata17 21 vddo 73 ad1 125 maddr9 177 mdata16 22 vsso 74 ad0 126 maddr8 178 mdata15 23 ad23 75 cbe0 127 maddr7 179 vsso 24 ad22 76 memclk 128 maddr6 180 vddo 25 ad21 77 vsso 129 maddr5 181 mdata14 26 ad20 78 sysclk 130 maddr4 182 mdata13 27 ad19 79 vsso 131 vsso 183 vddi 28 ad18 80 vddo 132 vssi 184 vssi pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 15 pin signal pin signal pin signal pin signal 29 vsso 81 clk25 133 vddi 185 mdata12 30 vddo 82 nc 134 vddo 186 mdata11 31 vssi 83 mdio 135 maddr3 187 mdata10 32 vddi 84 vddo 136 maddr2 188 mdata9 33 ad17 85 vsso 137 maddr1 189 mdata8 34 ad16 86 vssi 138 maddr0 190 vsso 35 cbe2 87 vddi 139 mcs3 * 191 vddo 36 vsso 88 mdc 140 mcs2 * 192 mdata7 37 req * 89 erst* 141 mcs1 * 193 mdata6 38 gnt * 90 vsso 142 vsso 194 mdata5 39 int * 91 vddo 143 vddo 195 mdata4 40 vddo 92 rxd3 144 mcs0 * 196 mdata3 41 vsso 93 rxd2 145 mrdy* 197 mdata2 42 ad15 94 rxd1 146 mrd* 198 vsso 43 ad14 95 rxd0 147 mwr3 * 199 vddo 44 ad13 96 rx_dv 148 mwr2 * 200 mdata1 45 ad12 97 rx_clk 149 vsso 201 mdata0 46 ad11 98 rx_er 150 vddo 202 mintr * 47 vsso 99 vddo 151 mwr1 * 203 tst* 48 vddo 100 tx_clk 152 mwr0 * 204 nc 49 ad10 101 tx_en 153 mgwe* 205 nc 50 ad9 102 txd0 154 mras * 206 nc 51 ad8 103 bias5v 155 vsso 207 vssi 52 cbe1 104 vsso 156 vddo 208 vddi all vdd and vss lines must be connected to the 3.3v supply and ground respectively. standard decoupling practices should be followed for proper device operation. the 4 pins marked as "nc" should be left as no-connects. they are intended solely for factory use. do not connect pins marked "nc" directly to either vdd or vss. if need be, the pins can be connected to either vdd or vss through a terminating resistor of value 1 k-ohm or greater. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 16 functional grouping the following diagram shows the functional grouping of the pm3351 signal pins. mcs[3:0]* pm3351 elan 1x100 md[31:0] mrd* idsel req* gnt* int* pciclk rst* clk25 mrdy* mmwr[3:0]* perr* serr* memclk ma[17:0] txd[3:0] tx_clk tx_en rxd[3:0] rx_dv rx_clk rx_er ad[31:0] c/be[3:0]* par frame* trdy* irdy* stop* devsel* mras* sysclk mintr* crs col mdc mdio mgwe* tst* local memory interface mii pci erst* pin description nomenclature: ? i input only ? o output only ? i/o bidirectional pin ? od output only, open drain (requires external pull-up resistor to vdd). the recommended pull-up resistance value for the open drain outputs is 2.7 k-ohm (this is the recommended pull-up value suggested for pci bus signals in the 5v signalling environment). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 17 pci expansion bus interface signal name size type description ad[31:0] 32 i/o multiplexed pci address/data bus, used by the pci host or the pm3351 to transfer addresses or data. cbe[3:0] 3 i/o command/byte-enable lines. these lines supply a command (during pci address phases) or byte enables (during data phases) for each bus transaction. par 1 i/o address/data/command parity, supplies the even parity computed over the ad[31:0] and cbe[3:0] lines during valid data phases; it is sampled (when the pm3351 is acting as a target) or driven (when the pm3351 acts as an initiator) one clock edge after the respective data phase. frame * 1 i/o bus transaction delimiter (framing signal); a high-to-low transition on this signal indicates that a new transaction is beginning (with an address phase); a low-to-high transition indicates that the next valid data phase will end the currently ongoing transaction. irdy * 1 i/o transaction initiator (master) ready, used by the transaction initiator or bus master to indicate that it is ready for a data transfer. a valid data phase ends with data transfer when both irdy * and trdy * are sampled asserted on the same clock edge. trdy * 1 i/o transaction target ready, used by the transaction target or bus slave to indicate that it is ready for a data transfer. a valid data phase ends with data transfer when both irdy * and trdy * are sampled asserted on the same clock edge. stop * 1 i/o transaction termination request, driven by the current target or slave to abort, disconnect or retry the current transfer. devsel * 1 i/o device acknowledge: driven by a target to indicate to the initiator that the address placed on the ad[31:0] lines (together with the command on the cbe[3:0] lines) has been decoded and accepted as a valid reference to the target's address space. once asserted, it is held asserted until frame * is deasserted; otherwise, it indicates (in conjunction with stop * and trdy * ) a target-abort. idsel 1 i device identification (slot) select. assertion of idsel signals the pm3351 that it is being selected for a configuration space access. req * 1o bus request (to bus arbiter), asserted by the pm3351 to request control of the pci bus. gnt * 1i bus grant (from bus arbiter); this indicates to the pm3351 that it has been granted control of the pci bus, and may begin driving the address/data and control lines after the current transaction has ended (indicated by frame * , irdy * and trdy * all deasserted simultaneously). int * 1od interrupt request. this pin signals an interrupt request to the pci host. the int * pin should be tied to the inta * line on the pci bus. perr * 1 i/o bus parity error signal, asserted by the pm3351 as a bus slave, or sampled by the pm3351 as a bus master, to indicate a parity error on the ad[31:0] and cbe[3:0] lines. serr * 1od system error, used by the pm3351 to indicate to the pci central resource that there was a parity error on the ad[31:0] and cbe[3:0] lines during an address phase. pciclk 1 i pci bus clock; supplies the pci bus clock signal to the pm3351. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 18 rst * 1i pci bus reset (system reset). performs a hardware reset of the elan 1x100 and associated peripherals when asserted. the rst* input uses a schmitt trigger to accommodate slow rise and fall times, allowing a simple rc network to be used to provide power-on reset capability. mii interface pins signal name size type description txd[3:0] 4 o mii transmit data. txd[3:0] is the nibble-wide mii transmit data bus. txd[3:0] transitions synchronously to the rising edge of tx_clk. if tx_en is asserted then the txd[3:0] bus has valid data which is to be accepted for transmission by the phy device. tx_en 1 o mii transmit enable. asserted by the pm3351 to indicate to the phy device that the txd[3:0] bus has valid data. tx_en is asserted with the first nibble of preamble and remains continuously asserted throughout the frame. tx_en is negated prior to the first tx_clk following the final nibble of the frame. tx_en is synchronous with respect to tx_clk. tx_clk 1 i mii transmit clock. tx_clk is a continuous clock that provides the timing reference for the tx_en and txd[3:0] signals output from the pm3351. tx_clk is a nibble rate clock; an mii transceiver operating at 100mbit/s must provide a tx_clk frequency of 25 mhz. for improved noise immunity this input buffer uses a schmitt trigger. rx_dv 1 i mii receive data valid. rx_dv is an input that indicates that the phy is presenting recovered and decoded nibbles on the rxd[3:0] pins. in order for a received frame to be accepted by the pm3351, rx_dv must be asserted prior to or coincident to the first nibble of the start of frame delimiter being driven on rxd[3:0]; it must remain continuously asserted until after the rising edge of rx_clk when the last nibble fo the crc is driven on rxd[3:0]. rx_dv is synchronous with respect to rx_clk. rxd[3:0] 4 i mii receive data bus. rxd[3:0] is the nibble-wide mii receive data bus. rxd[3:0] transitions synchronously to the rising edge of rx_clk. the pm3351 samples rxd[3:0] on every rising edge of rx_clk that rx_dv is asserted. rxd[3:0] is ignored if rx_dv is deasserted. rx_clk 1 i mii receive clock. rx_clk is a continuous clock that provides the timing reference for the rx_dv, rx_er, and rxd[3:0] signals input to the pm3351. rx_clk is a nibble rate clock; an mii transceiver operating at 100mbit/s must provide an rx_clk frequency of 25 mhz during frame reception. for improved noise immunity this input buffer uses a schmitt trigger. rx_er 1 i mii receive error. rx_er is driven by the phy for one or more rx_clk periods to indicate to the pm3351 that an error has occurred in the frame being received. the pm3351 samples rx_er on the rising edge of rx_clk only if rx_dv is asserted; all special code groups generated on rxd while rx_dv is deasserted are ignored. rx_er is synchronous with respect to rx_clk. crs 1 i mii carrier sense. crs is an input that indicates that the physical media is non- idle, either because of transmit or receive activity. in full-duplex mode crs is ignored. the phy is not required to have crs transition synchronously to either tx_clk or rx_clk. the pm3351 samples crs only on the rising edge of tx_clk . it is used as the carriersense variable in the mac deference process (see 802.3 spec clauses 4.2.8 and 22.1.3.2). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 19 col 8 i mii collision detect. col is an input that indicates that a collision has occurred on the physical media. in full-duplex mode col is ignored. the phy is not required to have col transition synchronously to either tx_clk or rx_clk. the pm3351 only samples col on the rising edge of tx_clk. mdio 1 i/o mii management data input/output.mdio is the bidirectional mii management port data pin. mdio is driven synchronously to mdclk and is sampled on the rising edge of mdclk. when a management frame is not being transferred, mdio is not driven. in order to implement the phy detection feature via the mii mechanical interface the mdio pin should be externally pulled down to vss through a 2.0- kohm +/-5% resistor. mdc 1 o mii management data clock. mdc is an aperiodic signal that is used as a timing reference for the mdio pin. mdc is continuously driven by the pm3351; it is asserted only during management frame activity. mdc uses the sysclk input as a timing reference. local memory interface although the on-chip local memory interface is designed to operate with various memory types the memories intended to be used with the pm3351 are -15ns sram and -150ns prom/eprom/eeprom. edo dram is supported for management and custom applications, but is not intended to be used for standard switching. signal name size type description mdata[31:0] 32 i/o memory data bus. mdata[31:0] carries the data driven to the external local memory by the pm3351 during local memory writes, and the data sent back to the pm3351 by the memory devices during local memory reads. in addition, configuration information is latched from the mdata[31:0] lines during elan 1x100 reset and loaded into an internal configuration register; either pullup-pulldown resistors or tristate buffers (enabled by the rst * input) drive configuration data on to the mdata[31:0] lines during reset. all mdata[31:0] pins have internal pullups. maddr[17:0] 18 o memory address bus; supplies a word-aligned address to the external memory devices (i.e., address bits 19 through 2 of the 24-bit byte address generated by the internal pm3351 logic), and thus select a single 32-bit word to be read or written. up to 1 mb of memory may be directly addressed in each bank using these address lines. mcs[3:0] * 4o memory bank chip selects. the mcs[3:0] * outputs select one of four memory banks (each bank has maximum depth of 4 megabyte). they are decoded directly from the most significant 2 bits (bits 23 and 22) of the 24-bit physical byte address generated by the internal pm3351 logic, and are synchronous to memclk. mras * 1o dram row address strobe output; supplies the row address strobe (ras) signal to one or more external dram banks. it is asserted to latch the row address (supplied on the maddr lines) into the dram array, and allow the column address to be output one cycle later. note- can be left as a no-connect output if not using dram. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 20 mrd * 1o memory read enable. this output signals the external memory banks that a read is being performed and data should be output on the mdata[31:0] lines from the specified address. the mrd* output may be tied to the oe* inputs of standard memory devices. mwr[3:0] * 4o memory write enables, used by the pm3351 to enable the data presented on individual byte lanes of mdata[31:0] to be individually written to memory. mwr[0] * corresponds to mdata[7:0], mwr[1] * corresponds to mdata[15:8], and so on. the mwr[3:0]* outputs should be connected to the appropriate byte write enables. mgwe* 1 o gobal memory write enable. this signal is used to signal that a write access is occurring, and should be connected to the we* inputs of dual cas asynchronous dram devices. note- can be left as a no-connect output if not using dram mrdy * 1i memory ready input. if an external memory timing generator is used, it can be connected to the mrdy * input to force the pm3351 to insert wait states into memory accesses. if the mrdy * line is deasserted, the pm3351 will hold the maddr[15:0], mcs[3:0] * , mrd * and mwr[3:0] * lines at their present values (as well as mdata[31:0] for memory writes).the mrdy* input is only sampled by the pm3351 when performing an sram-type access; it is ignored for all other memory types. this feature is not tested as part of the fuctional test program of the device. therefore, mrdy* must be tied low (to logic 0) to ensure correct operation. mintr * 1i local interrupt input. the mintr* may be used to provide an interrupt input to the elan 1x100 in special applications. if the mintr* input is not used it should be tied high. for improved noise immunity this input buffer uses a schmitt trigger. clock inputs and outputs signal name size type description sysclk 1 i 50 mhz master device clock input, this should be driven by a 50 mhz symmetrical clock source with a duty cycle between 40% and 60%. it is re-timed and driven out on the memclk line, and is also used in the internal device logic. for improved noise immunity this input buffer uses a schmitt trigger. memclk 1 o 50 mhz clock derived from sysclk; supplies the re-timed 50 mhz clock (input on the sysclk pin) to external devices. clk25 1 o 25 mhz clock output. the 50 mhz input clock is internally divided by two and output as a symmetrical 25 mhz clock on the clk25 output; this clock may be used as a clock reference input to an external phy device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 21 miscellanous inputs and outputs signal name size type description bias5v 1 i the 5 volt bias pin must be connected to 5.0 volts for the input and bi-directional pins to be 5 volt tolerant. this pin may be tied to vdd provided the maximum static signal level is below vdd + 0.3v. during power-up, the voltage on the bias5v pin must be kept equal to or greater then the voltage on all input pins to avoid damage to the device. in addition, the voltage on the bias5v pin is to be kept greater than or equal to the voltage on the vdd pins. tst* 1 i test select signal used for production testing. it must be tied high for correct operation. erst* 1 od external reset output. the erst* pin is driven low by the elan 1x100 to reset other components in the system. this output is asserted for a pre-set duration (10 milliseconds) upon the detection of a falling edge on the rst* input, or when the elan 1x100 senses a condition requiring a system hardware reset. it is an open-drain output, and should be pulled up using a 2.7k-ohm resistor. the erst* output may be tied directly to the rst* input to implement a debounce function in pushbutton reset applications. (note that the erst* output should be left unconnected in host-based applications where the elan 1x100 must not be allowed to reset the host cpu.) notes on pin description: 1. all inputs and bi-directionals present minimal capacitive loading and operate at ttl logic levels. 2. all digital outputs and bi-directionals have 2 ma d.c. drive capability. 3. pins mdata[31:0], mintr*, tst*, gnt*, and rst* have internal pull-up resistors. 4. the vssi and vsso ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the part. 5. the vddi and vddo power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the part. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 22 dc characteristics absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. parameter symbol value units supply voltage vdd -0.3 to +7.0 vdc bias5v pin voltage with respect to vss vbias5v minimum: vdd C 0.3v maximum: 5.5v vdc input voltage vin v bias5v +0.3 vdc input current iin +/-10 madc static discharge voltage 1000 v latch-up current 80 ma lead temperature +220 c storage temperature tst -45 to +125 c junction temperature tj +125 c recommended operating conditions parameter symbol value unit s min nom max supply voltage vdd +3.13 +3.30 +3.47 vdc bias5v voltage vbias5v +4.75 +5.0 +5.25 vdc operating ambient temp. ta 0 +70 c note: the pm3351 has been characterized over the industrial temperature range (ta = -40c to +85c). all dc and ac parametrics met the limits presented in the following tables. in addition the package thermal characteristics of the 208 pin pqfp package and power consumption of the device are such that the device can be operated without any forced air (i.e. still air) over the full commercial temperature range; however, if operating over the industrial temperature range (which has a maximum ambient temperature of +85 c) a minimum airflow of 100 linear feet per minute is required. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 23 d.c. characteristics dc characteristics are specified over recommended operating conditions (t a = 0c to +70c, v dd = 3.3 v 5%, v bias = 5.0v 5%). parameter description ttl i/os pci i/os units min max min max vih input high voltage 2.0 vdd+0. 5 2.0 vdd+0. 5 vdc vil input low voltage -0.5 0.8 -0.5 0.8 vdc voh output high voltage (vdd = min, i oh = -2 ma, note 2) 2.4 vdd 2.4 vdd vdc vol output low voltage (vdd = min, i ol = -2 ma, note 2) 00.400.4vdc lil input low leakage current, note 3 -10 10 -10 10 a lih input high leakage current, note 3 -10 10 -10 10 a lilpu input low current (pull ups, v il = gnd, note 4) +100 +20 a lihpu input high current (pull ups, v ih = vdd, note 4) -10 +10 a lddop supply current, vdd = 3.47 mhz, outputs unloaded, sysclk = 50mhz 450 ma notes on d.c. characteristics: 1. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 2. output pin or bidirectional pin. voh not measured on open drain outputs. 3. input pin or bidirectional pin without internal pull-up resistor. 4. input pin or bidirectional pin with internal pull-up resistor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 24 ac characteristics ac characteristics are specified over recommended operating conditions (t a = 0c to +70c, v dd = 3.3 v 5%, v bias = 5.0v 5%). the pm3351 only supports a 5v signalling environment. notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are specified with a 50 pf load on the outputs, unless otherwise noted. 3. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to 300mv of the termination voltage on the output. the test load is 50 w to 1.4v in parallel with 10 pf to gnd. notes on typical values ac parameters shown as typical in the following tables are tested for functionality under typical conditions. no guarantees are implied for maximum or minumum performance. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 25 pci bus interface parameter description min typ max units tpsu setup time of all pci inputs from pciclk rising 7 nsec tph hold time of all pci inputs from pciclk rising 1 nsec tpon minimum float to active delay of all outputs from pciclk rising 2 nsec tpoff maximum active to float delay of all outputs from pciclk rising 28 nsec tpval signal valid of all outputs from pciclk rising 2 13 nsec trstoff rst* active to output float delay 40 nsec notes: (1) pci inputs are considered to be those signals that are driven by an external pci device, while pci outputs are signals that are driven by the pm3351. note that many of the pci signals are treated as outputs in some cycles and inputs in others. pci bus interface timing pciclk pci inputs pci outputs tpsu tph tpon tpval tpoff pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 26 mii interface parameter description min max units ftsc tx_clk frequency 0 25 mhz ttch/ttcl tx_clk duty cycle (high/low) 35 65 percent ttod output delay from tx_clk rising to txd[3:0], tx_en 020nsec txd[3:0], tx_en mii interface transmit signals ttod ftsc tx_clk parameter description min max units frpc rx_clk frequency 0 25 mhz trch/trcl rx_clk duty cycle (high/low) 35 65 percent trpsu rxd[3:0], rx_dv, rx_er setup to rx_clk 8 nsec trph rxd[3:0], rx_dv, rx_er hold to rx_clk 8 nsec rxd[3:0] rx_dv, rx_er mii interface receive signals frpc rx_clk trpsu trph trpsu trph pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 27 parameter description min typ max units tmdch min mdc high pulse width (cload = 390 pf) 1 160 nsec tmdcl min mdc low pulse width (cload = 390 pf) 1 160 nsec tmdcp min mdc period (cload = 390 pf) 1 400 nsec tmdo1 min mdio (output delay) to posedge mdc 1 cload = 470 pf. measured from vil,max (0.8v) or vih,min(2.0v) 20 nsec tmdo2 min mdio (output delay) to posedge mdc 1 cload = 470 pf. measured from vil,max (0.8v) or vih,min(2.0v) 20 nsec tmdisu min mdio (input) to mdc setup time 100 nsec tmdih min mdio (input) to mdc hold time 0 nsec notes: 1. tested at 50 pf in production test and derated. mdc mii management data signals mdio, as output mdio is driven by pm3351, sampled by phy mdio, as intput mdio is driven by phy, sampled by pm3351 tmdo1 tmdo2 tmdih tmdisu tmdch tmdcl tmdcp pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 28 memory interface 15 ns sram ac timing parameter description min typ max units tckp mclk period 20 ns tmaod maddr[17:0] delay from sysclk (read, first cycle) 21 ns tcew mcs*[3:0] pulse width 35 ns toew mrd* pulse width 35 ns tmdis mdata[31:0] setup to sysclk (read, second cycle) 4ns trdh mdata[31:0] hold from mrd* rise (read, second cycle) mdata[31:0] hold from mcs*[3:0] rise (read, second cycle) 0ns twaw maddr[17:0] setup to mwe*[3:0] rise 20 ns twah maddr[17:0] hold from mwe*[3:0] rise 0 ns twp mwe*[3:0] pulse width (write, second cycle) 15 ns twds mdata[31:0] setup to mwe*[3:0] rise 8 ns twdh mdata[31:0] hold to mwe*[3:0] rise 0 ns sram tim ing: read/w rite cycle mclk tc k p s y sc lk mrdy * mwe* [ 3:0 ] mcs[n]* don't care undefined mrd * to e w tc e w addr[17:0] m data[31:0] a2 d2 a1 tw d h d1 tm d is trdh tw d s tm a o d tmmd tm r w n o tes: (1) the functional w aveform s above are consistent w ith no w ait states inserted. (that is, w ith m r d y* being ttl low during the read cycle). the m r d y* tim ing w aveform is show n to highlight th e tim in g p aram eter m easurem ents tc e w tw p tw a h tw a w read cycle 1 read cycle 2 write cycle 1 write cycle 2 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 29 150 ns eeprom/eprom ac timing parameter description min typ max units tckp mclk period 20 ns tmaod max maddr[17:0] delay from sysclk (read, first cycle) 21 ns tcew min mcs*[3:0] pulse width 190 ns toew min mrd* pulse width 190 ns tmdis min mdata[31:0] setup to sysclk (read, 11th cycle) 10 ns trdh min mdata[31:0] hold from mrd* rise (read, 12th cycle) (by design, data is latched internally in the cycle before the rise of mrd*) 0 ns twaw min maddr[17:0] setup to mwe*[3:0] rise 190 ns twah min maddr[17:0] hold from mwe*[3:0] rise 40 ns twp min mwe*[3:0] pulse width (write, second cycle) 190 ns twds min mdata[31:0] setup to mwe*[3:0] rise 180 ns twdh min mdata[31:0] hold to mwe*[3:0] rise 15 ns eeprom/eprom write cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tw aw tw p tw ds tcew tm aod tw ah tw dh 0ns 100ns 200ns 3 0 sysclk mclk m w e *[3 :0 ] m c s *[3 :0 ] mrd* addr[17:0] m data[31:0] pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 30 eeprom/eprom read cycle edo dram (not used in standard switching applications) 60 ns edo dram ac timing parameter description min typ max units tckp mclk period 20 nsec tard min row address stable to mras* fall delay 15 nsec traw min row address width 35 nsec tacd min column address stable to cas* fall delay 15 nsec tcaw min column address width 35 nsec tcp min cas* period 35 nsec tcpl min cas* low time 15 nsec twds min write data setup to cas* fall 15 nsec twdh min write data hold to cas* fall 15 nsec trds min read data setup to cas* fall 20 nsec trdh min read data hold from cas* fall 0 nsec trec min read data hiz to write data drive 15 nsec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tce toe tmao tmdi trd 0ns 100n 200n 3 syscl mcl mw e*[3: mcs*[3: mrd maddr[17: mdata[31: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 31 maddr[19:0] mras* mcs[n]* mrd* mdata[31:0] row col1 col2 col3 col4 d1 d2 d3 d4 tard tacd tcp traw tcaw don't care undefined trds drp / 12-96 maddr[19:0] mras* mcs[n]* mwr[3:0]* mdata[31:0] row col1 col2 col3 d1 d2 d3 d4 maddr[19:0] mras* mcs[n]* mwr[3:0]* mdata[31:0] row col1 col2 d2 notes: (1) pin definitions shown above are for single cas dram. dual cas dram is supported by selecting the mdcas bit in the memory configuration register. in this mode, the cas signals are driven by mwe*[3:0] and the ras signals are driven by mcs*[3:0]. (2) asserting the mslo bit in the memory configuration register extends the cas low time to support 80 ns dram mrd* d1 col4 4-word burst read 4-word burst write 1-word read followed by write trec tcpl mclk mclk tckp tard tacd tcp traw tcaw tcpl tckp tw ds tw dh mclk tckp tard tacd tcp traw tcaw tcpl trdh tw ds tw dh 60 ns sin g le cas edo dram pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 32 clocking parameter description min typ max units fck sysclk frequency 1 5 50.0 50.5 mhz tch sysclk high pulse width 8nsec tcl syclk low pulse width 8nsec fpck pciclk frequency 2 0 40 40.5 mhz tpch pciclk high pulse width 11 nsec tpcl pciclk low pulse width 11 nsec fck25 clk25 frequency 3 fck/2 mhz trst rst* active time after pciclk and sysclk stable 10 usec notes: 1. the minimum clock frequency for production test is 5 mhz. in actual operation, the minimum sysclk frequency is 1 mhz if dram present (this is to refresh local dram memory); otherwise the minimum sysclk frequency is 0 mhz, reflecting completely static operation. the nominal frequency of 50 mhz must be provided for full throughput. 2. the minimum clock frequency for pciclk reflects completely static operation. the nominal frequency of 40 mhz must be provided for full throughput. minimum production test at 5.0 mhz 3. guaranteed by design. miscellaneous parameter description min max units tmisu mintr* setup to posedge sysclk 10 nsec tmih mintr* hold to posedge sysclk 0 nsec pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 33 functional description overview this section will provide an overview of the pm3351 elan 1x100 components, the device initialization and configuration process, the structures built and used by the device to perform its functions, and a brief description of how packets are switched by the device. system components in order to describe the functions and operation of the elan 1x100 device, it is first necessary to discuss the operating environment that is intended to be built around it. a typical simple switching subsystem utilizing the elan 1x100 device consists of: 1. the elan 1x100 device itself. (clearly, a complete system will include more than a single elan 1x100 device, but this is not shown in the diagram below.) 2. a set of sram devices that provide the operating memory for the elan 1x100. this memory should be mapped to the lowest bank of the elan 1x100 address space (i.e., addresses starting at 0x000000 hex). the amount of sram provided is a system-dependent parameter; a minimum system with about 150 kb of buffer space and around 1200 mac addresses in the address table requires 512kb of sram. sram requirements for this and other system configurations may be computed using parameters supplied later in this document. 3. an eprom containing the bootstrap image for the elan 1x100 (i.e., the operating firmware, operating parameters, and system initialization code) if this elan device is designated as the system master. this eprom is mapped to the second lowest bank of the elan 1x100 memory address space (the 4 mb address range starting at address 0x400000 hex.) the size of the eprom is highly dependent on the operating configuration of the elan 1x100, with the minimum requirement being 32 kb. 4. external transceiver devices that implement the phy layer functions required for 100baset ethernet. 5. an led register, connected to a bank of eight leds, that may be used to report status information for diagnostic purposes if required. the led register is mapped into the third bank of elan 1x100 memory address space, starting at 0x800000 hex. 6. a system voltage monitor or other means of asserting a system reset for a specified time after the power supply voltage has stabilized, plus, if desired, a pushbutton switch for forcing a system reset after power-up. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 34 7. a set of pull-up and pull-down resistors that are connected to the elan 1x100 data bus in order to drive device configuration information on to the data bus during system reset. note that the above subsystem description details a single elan 1x100 device in the system. this subsystem is expected to work in tandem with similar elan 1x100 or elan 8x10 subsystems to create an actual switch; however, the fundamental system operation does not change as additional elan compatible devices are added. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 35 system block diagram the following diagram represents a high-level view of the simple switch subsystem described above: elan 1x100 pm3351 power-on reset led register eprom sram device config pull-up/ pull-down resistors rst* erst* txd[3:0] tx_en tx_clk rxd[3:0] rx_dv rx_clk rx_er crs col mdc 50 mhz clock sysclk mdata[31:0] maddr[17:0] mrd, mwr[3:0] mcs[0] mcs[1] mcs[2] d a r/w cas* d a oe* cs* mdata[7:0] pci bus mdata[7:0] mdio col[7:4] in the diagram above, the phy device, the eprom, the sram and the 50 mhz clock oscillator are all implemented in a straightforward manner from off-the-shelf parts. the device configuration resistors are merely resistor pull-ups and pull-downs that drive the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 36 memory data bus lines to specific values during reset, as described later; the resistor values used are not critical, and may range from 4.7k to 10k. it is assumed that the minimum recommended configuration of 512 kilobyte of sram and 32 kbytes of eprom are used. a typical implementation would use four 128k x 8- bit 15 ns sram, together with a 256 kbit (32k x 8-bit) 150 ns eprom. larger memories may also be used if more buffer space or mac addresses are to be supported; if this is done, the configuration parameters in the eprom must be changed to reflect the increased memory size. the sram and eprom device types and speeds are defined by the setting of the pull-up / pull-down resistors on the memory data bus during reset time. the power-on reset generator can be created either from discrete components, or from a low-cost cpu monitor; the erst* output from the elan 1x100 chip is strapped to the reset signal to implement the watchdog capability of the elan device. note that the erst* output may, as an alternative, used to signal some external processor that the elan 1x100 device has encountered a fatal error condition requiring a software or hardware reset; in this case, the erst* output should be pulled up using a 2.7k resistor. the led register is implemented using a simple 8-bit ttl register with a clock enable that is tied to the indicated chip select output from the elan 1x100. eight leds may be connected to the outputs of this register to present the diagnostic status codes output by the elan 1x100 firmware during self-test, system boot and operation. if a simple ttl register is used, the led register is effectively write-only; writes to this register will modify the state of the leds, but reads from this register return invalid values. a read- back register can be used if this is a significant issue. the first three chip select lines from the elan 1x100 (i.e., mcs[0]*, mcs[1]* and mcs[2]*) are tied to the sram, the eprom and the led register, respectively; the remaining chip select is unused. this maps the sram into the first bank of address space, the eprom into the second bank, and the led register into the third bank. the address map in the following subsection gives the 24-bit address ranges assigned to each resource. this system has only been presented to serve as a basis for the following discussion on the device and system operation, and is not intended to serve as a complete example or reference design. more details on actual system construction with the elan 1x100 may be found in the relevant application notes and reference design documents. system memory map the elan 1x100 device uses a single linear (flat) byte-addressable 16 mb address space for accessing memory and memory-mapped devices. the external memory map for the system described above is quite straightforward. from the point of view of the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 37 local memory bus, it is as follows (note that the memory addresses shown increase upwards): 0xffffff unused bank 3 0xc00000 0xbfffff unused bank 2 0x800004 0x800000 led register 0x4fffff unused 0x420000 bank 1 0x41ffff boot eprom (32 kb; occupies 128 kb) 0x400000 0x3fffff unused 0x100000 bank 0 0x07ffff system sram (512 kb) 0x000000 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 38 note that the 32 kb boot eprom actually occupies 128 kb of address space. this is because the eprom is only 8 bits wide (i.e., a 32k x 8-bit configuration), and so is connected to the least significant byte lane of the memory data bus. hence each byte of the eprom takes up a full 32 bits worth of address space, leading to the 128 kb requirement. in a similar manner to the 8-bit wide eprom, the led register is mapped to the least significant 8 bits of the data bus, but takes up a full 32 bits of address space. no other device is shown as being mapped to the elan 1x100 address space in this simple and minimal system; however, other devices (such as rs232-c serial ports) may be interfaced as well, provided that firmware is developed to support them. when viewed from the pci bus, the elan 1x100 device appears to take up a 16 mb block of contiguous addresses in the total 4 gb pci address space. a virtually identical memory map is presented to the pci bus when accessing the elan 1x100 device as a pci slave (target), with the exception that a set of device control and communication registers are implemented in the uppermost 64 kb of the 16 mb address space used by the elan 1x100 device (note that the memory addresses shown increase upwards): rest of pci address space 0xbbffffff device control registers 0xbbff0000 0xbbfeffff unused bank 3 0xbbc00000 0xbbbfffff unused bank 2 0xbb800004 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 39 0xbb800000 led register 0xbb4fffff unused 0xbb420000 bank 1 0xbb41ffff boot eprom (32 kb; occupies 128 kb) 0xbb400000 0xbb3fffff unused 0xbb100000 bank 0 0xbb07ffff system sram (512 kb) 0xbb000000 rest of pci address space the start address of the block occupied by the elan 1x100 is defined by the setting of the memory base address register within the pci configuration register space of the elan 1x100 device, and is represented by the bb component of the addresses given in the table above. the memory base address register may be set to any arbitrary value via a pci configuration write after system reset, provided that the base address is on a 16 mb boundary and that the elan 1x100 operating firmware parameters are set consistently with the selected base address. alternatively, the base address may be set to a value between 0x00 and 0x0f, during reset, by the configuration registers pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 40 device internal blocks the elan 1x100 consists of the following major components: a switch processor, one 100mbit/s full-duplex mac interface, a dma controller, a memory controller and a pci expansion port. switch processor the switch processor is a 50 mhz proprietary risc cpu that executes the firmware required for carrying out all the frame switching and device control functions of the elan 1x100. it is specifically designed to support lan protocols at high speeds in a closed embedded system environment. the switch processor contains various hardware features that permit it to carry out all of its functions at maximum efficiency, and is tightly coupled to the rest of the elan 1x100 device logic. the switch processor interfaces to the rest of the elan 1x100 device via several dedicated hardware ports: it uses a special control register access bus to read or write any of up to 96 16- bit control registers that are implemented by the internal hardware units; these registers are used to set configuration parameters in various elan 1x100 units, read the unit status, set various operating parameters (such as address pointers), and perform device self-test. it implements a set of thirteen level-sensitive hardware interrupts that are connected to various blocks within the elan 1x100; these interrupts are the primary task dispatching entity for the base switching code. assertion of an interrupt line causes the corresponding interrupt service routine (isr) to begin executing, and execution normally proceeds until the isr has finished servicing the unit that required attention. a set of 32 general-purpose outputs and 15 general-purpose inputs are provided. these are connected to various low-level control and status signals presented by various elan 1x100 internal logic blocks. the general-purpose inputs and outputs considerably speed up the testing of the state of the logic blocks and also the control of their functions, as multiple tests on inputs or multiple modifications of outputs can be performed in a single instruction. a set of 16 coprocessor condition tests are implemented by the switch processor. these inputs are used to signal high-level device conditions generated by various elan 1x100 functional units to the switch processor firmware. the internal and external registers implemented by the switch processor and the associated elan 1x100 functional units, as well as the view of the debug registers from the pci bus interface, are presented in subsequent sections. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 41 the switch processor expects to locate its operating firmware as part of a boot image present in the external memory space. the format of the boot image is described later. 100mbit/s ethernet mac interface a complete ethernet/ieee mac-layer interface is built into the elan 1x100 chip, communicating with external 100 mbit/s transceivers via the on-chip mii port. the mac- layer interface logic performs most of the processing tasks required by the ieee standard in hardware. in addition, the mac interfaces contain fifo buffers that enhance throughput and reduce bandwidth loss due to frame delays. the mac layer interfaces also permits loopback testing of the external transceiver. the pm3351 also supports the mii management interface to an mii compliant phy device. this is accomplished by using the mii serial management pins (mdio and mdclk) in conjunction with firmware on the switch processor. this allows the pm3351 to support auto-negotiation, link status, and other management operations on the attached phy device(s). at system initialization time, the switch processor polls the phy device to determine the starting configuration resulting from the autonegotiation process, prior to beginning normal operation; thereafter, the switch processor periodically re-interrogates the phy device to determine whether the configuration is still valid, or whether a configuration change has occurred. the elan 1x100 performs only the 802.3 mac-sublayer functions and provides a simple, inexpensive interconnection to an attached physical layer (phy) device through the medium independent interface (mii) as described in 802.3u, clause 22. the attached 100mbit phy device is responsible for performing the physical coding sublayer, physical medium attachment, and physical medium dependent sublayers; that is, it is the interface between the actual ethernet media on one side and the mii interface on the other side. the mac interface unit consists of the following functional blocks: a signal interface compliant with the mii logical and electrical specifications. the interface communicates with the phy device using the txd[3:0], txen and tx_clk signals for transmit data, and the rxd[3:0], rx_dv, rx_er and rx_clk signals for receive data. in addition, the crs and col signals are used for medial access during half-duplex operation. note that the tx_er signal is not directly supported by the elan 1x100; the tx_er input on the phy device, if present, should be tied low.1 1 the elan 1x100 does not provide a tx_er signal as the device, being store-and-forward, will never transmit an errored frame; in addition, the logical implementation is such that it is impossible to have a data starvation condition occur during transmit. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 42 a series of two unidirectional buffer fifos for receiving data from the mii media: the first is a 32-deep nibble-wide fifo that receives framed nibbles from the mii receive channel pins; the second is the primary 64 byte receive fifo that assembles the nibbles into 32-bit data words and buffers them prior to transfer to the external sram. additional control logic is provided to strip off the preamble and start frame delimiter (sfd) from the receive data, to assemble the framed data nibbles into octets, and to perform clock synchronization between the mii receive clock and the internal system clock. the assembled and buffered data words are then passed to the dma controller, which in turn writes them out to local memory. note that the mac interface unit can begin receiving the next incoming frame while the dma is still servicing the previous frame; control information is inserted into the fifos to ensure that the two frames are properly separated before transfer to memory. a 2048-byte transmit fifo is provided to buffer transmit data received from other elan devices over the pci expansion bus interface prior to transmission on the mac transmit channel. this fifo is large enough to hold more than one maximum sized frame of 1518 bytes (plus an additional 512 bytes of the next frame), or up to 32 minimum sized (64-byte) frames, allowing frames to be stacked back-to-back for continuous transmission in the presence of pci bus latencies. frame transmission on the mii port only starts if an entire frame is present in the transmit fifo, and the switch processor has indicated that the frame is to be transmitted. during transmission, data octets are read from the transmit fifo by the transmit mac interface logic, synchronized to the mii transmit clock, and then output on the mii transmit data nibble pins. additional logic in the transmit interface implements the lower-level frame transmission process described in the 802.3 specification (preamble and sfd insertion, interframe gap timing, collision detection and carrier deference for half-duplex, etc.). control/status registers and logic that allows the switch processor to control the mac port and the attached phy devices, and also to monitor status. the control/status registers contain the timers required for the csma/cd algorithm. mac transmit sequence during transmission, 8-bit data octets to be transmitted are passed from the transmit fifo to the link transmit interface where they are synchronized to the mii transmit clock (tx_clk). after any required deference or interframe gap time, the mii framing signal tx_en is asserted and the preamble and sfd are sent on the txd[3:0] pins. after the sfd, the data octets comprising the ethernet frame header and payload are disassembled into nibbles, which are then transmitted on the txd[3:0] pins, followed pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 43 ultimately by the frame check sequence (fcs) word. the mac interface unit will then insert an interframe gap before proceeding to the next frame. a 2-part interframe gap timing algorithm (functioning according to the ieee 802.3 specification) is implemented. if a two-part interframe gap is not desired, it is possible to set the part 1 timing to zero, in which case the device will implement the ethernet v2.0 (blue book) interframe gap behavior. the mac logic also implements an internal jabber counter to time out excessively long transmissions; thus the elan 1x100 does not require the external phy to provide jabber protection. half-duplex normal collision in full-duplex mode, the mii signals col (collision detect) and crs (carrier sense) are treated as don't cares, and have no affect on frame transmission and reception. in half- duplex mode, however, the col and crs signals are used by the mac transmit logic to implement the required collision sensing and deference processes as outlined in the 802.3 specification. if a collision is detected (as reported by the external phy on the col pin) prior to the first 512 bits of the frame being transmitted, a normal collision is declared. the mac port immediately ceases frame data transmission; instead, it forces transmission of a 32-bit (8-nibble) jam sequence, flushes the transmit data disassembly registers, and signals to the switch processor that a collision has occurred, as well as an indication that a normal collision was detected. the jam sequence used by the mac is a series of 8 nibbles with txd[3:0] of 5 hexadecimal (0101 binary). in response to the collision indication, the switch processor will load an internal backoff timer with the appropriate pseudorandom value that denotes the backoff time to be counted out by the mac transmit logic. when the backoff period is timed out, the mac logic will automatically re-attempt transmission of the frame, which will be retained in the transmit fifo. if sixteen transmission attempts of a single frame have ended in collisions, however, the switch processor will discard the frame and clear it from the transmit fifo. half-duplex late colsion a late collision is declared if the collision was detected after 512 bits of the ethernet frame, including the preamble and sfd, had already been transmitted. in this case, the mac will abort the transmission of the frame and send the jam sequence as usual, but the switch processor will (upon notification of a late collision) cause the frame to be dropped from the transmit fifo and not retried. this is required as a consequence of the dynamic re-allocation of space within the transmit fifo; once more than 64 bytes of a frame have been transmitted (i.e., the late collision threshold has been crossed), the space occupied by the transmitted portion of the frame in the transmit fifo will begin to be continuously deallocated and used to fetch and buffer the next frame. as a result, a pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 44 late collision will usually preclude the retransmission of the original frame data, as it is no longer present within the fifo. mac receive sequence data nibbles are received from the mii receive data signal pins (rxd[3:0], in conjunction with the clock, framing and error signals) and assembled into 8-bit data bytes, which are then written to the receive fifo. the data words in the receive fifo is subsequently read out by the dma controller as a stream of 32-bit words, and transferred to buffers in the external memory. at the end of frame reception, the mac logic provides the dma controller with the received frame status: frame too long (i.e., the received frame exceeded the configurable maximum frame size), frame too short (i.e., the frame length was below the configurable minimum frame size), misaligned frame (a framing error was detected during nibble-to-byte conversion), or fifo overrun (data was lost because the receive fifo was not drained at a sufficiently high rate). the dma controller combines this status with its own internally generated error conditions when supplying the switch processor with the general received frame status. oversize receive frames are truncated by the mac logic to prevent buffer exhaustion during the reception of a jabber. assertion of the mii rx_er signal while rx_dv is asserted will force a crc error if the data portion of the frame is being received, and will cause the frame to be dropped if the preamble or sfd is being received. the elan 1x100 mac interface is configurable via a set of configuration registers that are loaded at initialization time. the following parameters are configurable: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 45 parameter min max units default numeric setting value interframe spacing, part 1 0 255 nibble times 1 15 60 bit times interframe spacing, part 2 0 255 nibble times 9 36 bit tmes preamble length (not including sfd) 0 255 bits 52 56 bits collision jam length 0 255 byte times 4 32 bits maximum receive/transmit frame size 0 2048 bytes 1518 1518 bytes minimum receive frame size 0 255 bytes 64 64 bytes late collision threshold 0 255 byte times 64 512 bit times receiver blind time 0 255 nibble times 0 0 bit times frame type recognition the mac interface (in conjunction with the dma controller receive channel and the switch processor) also allows selected frames to be received and specially handled by the elan 1x100, based on the ethertype field within the frame. (note that this capability applies only to frames coded according to the ethernet v2.0 standard, not the ieee 802.3 standard with llc coding.) this facility can be used, for example, to separate address resolution protocol (arp) frames from normal tcp/ip traffic, or for recognizing and diverting mac control frames for flow control and other purposes. the frame type recognition capability is implemented using a 16-bit register, referred to as the etype register, which is used to compare the ethertype fields of all received frames to a predefined value. if a match is found, an indication is passed to the switch processor by the dma controller at the time that the former is notified of the presence of the received frame. the etype register is normally set to 0x8808 hex after system reset (i.e., the ethertype value corresponding to full-duplex mac control frames as per ieee 802.3x, clause 31); the switch processor may, however, modify this register if some other type is to be recognized. note that only one etype register is provided, and hence only one ethertype value may be checked for at any time. (additional type checking is performed by the switch processor firmware as required.) half-duplex flow control: backpressure flow control is supported as an option during half-duplex operation by means of a backpressure mechanism, activated by the switch processor when an out-of-buffers condition is detected during a high volume of received traffic. backpressure is 1 a nibble time is one rx_clk or tx_clk period on the mii interface (nominally 40 ns). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 46 implemented by the mac logic by continuously transmitting an extended jam sequence (all-zeros) pattern, with gaps of one standard interframe spacing inserted periodically to prevent the backpressure pattern from being interpreted as a jabber. collisions encountered during backpressure will not cause the mac channel logic to back off in the normal manner; instead, the mac channel will send the standard jam pattern, time out a normal interframe gap, and then resume the backpressure pattern. if, during backpressure, the mac channel detects that one or more frames are ready to be transmitted over the channel by the elan 1x100 (e.g., a frame was received over the pci expansion bus and is destined for an end-station on the flow-controlled channel), the mac channel will cease transmitting the backpressure pattern, wait for a normal interframe gap, and then transmit the desired frame(s). after all the pending frames have been transmitted, the mac logic will resume backpressuring the channel. the backpressure mechanism described above is an optional feature: it should be noted that this backpressure method will result in the complete shutdown of the mac channel (i.e., even local segment traffic will not be allowed to proceed), and so it is recommended that backpressure be enabled only on ports that are connected to a small number of end-stations. full-duplex flow control: pause mac control frames backpressure flow control relies on collisions to shut off frame reception, and hence cannot be used during full duplex operation. pause mac control frames, as specified in ieee 802.3x, annex 31b, are employed instead. pause frame transmission is controlled by the switch processor: if the switch processor determines that the amount of available receive buffer space has fallen below a threshold, it will initiate the transmit of a mac control frame that is formatted as a pause frame according to the ieee 802.3x standard, with a "pause_time" field set to a configurable number of slot times (nominally 100). additional pause frames, with the same pause timer value, are transmitted if the condition persists after the pause period ends. the mac logic also supports full duplex flow control attempts by downstream entities when they are unable to accept data transmitted by the elan 1x100. in this case, pause frames are received with their ethertype fields set to 0x8808 hexadecimal, indicating a mac control frame. the switch processor will then verify that the frame is valid, shut off frame transmission at the next inter-frame boundary, and time out the requested pause time (using a software-based method). if no more pause frames are received before the pause timer expires, transmission will recommence. clk25 the elan 1x100 provides a clk25 output that can be tied directly to the 25 mhz input clock used by most 100 mbit/s ethernet phy devices. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 47 multichannel dma controller the on-chip dma controller contains four independent and concurrently operating channels: two for the 100 mbit/s mii port (one for receive and one for transmit) and two dedicated to the 1 gbit/s expansion port. the dma controller, operating under the control of the switch processor, is responsible for performing all data block transfers within the elan 1x100 made between the mii port, the local memory and the expansion port. the dma controller also computes 32-bit ieee frame check sequence (fcs) remainders over the received and transmitted frames, allowing the switch processor to filter frames with crc errors on receive, and also allowing crcs to be computed for injected management frames on transmit. in addition, the dma controller implements an address lookup process that attempts to map the 48-bit mac addresses of received frames to entries in an address table maintained in local memory. the dma controller provides sufficient bandwidth to guarantee that there will be continuous and uninterrupted reception and transmission of frames at full wire rates. a special feature of the dma controller is its ability to automatically allocate buffer storage from a central free pool (organized as a linked-list pointed to by a dedicated device register) these allocatable data structures are called packet buffers ; they are of fixed (and configurable) length, and are chained together into linked-lists to hold ethernet frames of different lengths. the dma channel associated with the receive path is capable of creating these linked-lists of packet buffers automatically whenever frames are received. the four dma controller channels are dedicated to various functions as follows: one channel (referred to as the receive channel) is used to perform data transfers between the mac receive fifo and the local memory, copying received frame data from the fifo to the local memory. as mentioned, the receive channel generates a linked-list of packet buffers in external memory, automatically allocating packet buffers as needed from a central free pool. a 32-bit crc is computed on the receive data transfers, and the crc result is accessible to the switch processor firmware in the form of a crc error status bit after a frame has been received. one channel (referred to as the transmit channel) is used to perform block transfers over the external pci expansion bus from external devices (other elan 1x100s, elan 8x10s, or any other device implementing the same protocol) to the 2048-byte transmit fifo. this channel can follow a chain of remote source packet buffers, reading data over the pci bus. only the required frame data is written into the transmit fifo; the headers of the packet buffers are stripped off by the channel transfer logic. the transmit channel implements special logic that allows the switch processor to inspect the frame header and determine how the frame should be treated after it has pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 48 been read into the transmit fifo. this consists of a small 16-entry queue (referred to as the disposition fifo), that holds disposition commands generated by the switch processor. after the header of each frame has been read over the pci expansion bus, the transmit channel notifies the switch processor via an interrupt; the switch processor is then responsible for checking the header data and writing a disposition command into the disposition fifo. the disposition command instructs the transmit channel logic as to how the frame should be handled. in all cases, a disposition command applies only when a frame has been completely read into the transmit fifo, and the first byte of the frame reaches the head of the transmit fifo. the purpose of the disposition fifo is to improve the efficiency of the switching firmware when handling transmit frames. each entry in the disposition fifo corresponds to a specific frame that has been placed into the main 2048-byte transmit fifo, and indicates how that frame is to be dealt with. three possible actions may be requested by the firmware, by setting entries in the disposition fifo to various codes: 1. send: the frame can be automatically sent over the mac port when it reaches the head of the transmit fifo, i.e., the preceding frame, if any, has been deleted from the fifo. this is the normal mode of operation, used for dealing with frames that should be transmitted without special processing. 2. drop: the frame can be simply deleted from the transmit fifo when it reaches the head of the fifo, without transmitting it over the mac port. this is used when the elan 1x100 decides to reject a particular frame that was queued for it from an external device, or for special firmware-controlled frame processing. 3. stop: when the first byte of the frame reaches the head of the transmit fifo, the dma controller should stop reading any more data out of the transmit fifo, and instead interrupt the switch processor. the switch processor firmware may then choose to read data out of the transmit fifo if required; when the firmware processing is done, the disposition fifo entry may be changed to a drop code to delete the frame from the transmit fifo, or to a send code to transmit the frame over the mac port in the normal manner. the use of the disposition fifo permits the firmware to make early decisions about how the frame should be handled, even before the frame has been completely read into the transmit fifo. these decisions are expressed in the form of the disposition codes (send, drop, and stop), which travel down the disposition fifo in lockstep with the stored frames travelling down the transmit fifo. the dma controller ensures that one entry is read from the disposition fifo for each frame that is read out of (or dropped from) the transmit fifo. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 49 one channel, referred to as the pci access channel, is used to perform block transfers under control of firmware running on the switch processor. this channel is capable of performing pci configuration read or write transactions as well as standard pci memory read or write operations. it is not intended to handle frame data, but is generally used for control and inter-device communication functions. the last channel (referred to as the transfer handshake channel) facilitates the frame exchange handshake that takes place between multiple pm3350 and pm3351 devices across the pci expansion bus this channel can be set up to perform up to seven writes in a single series of pci transactions to special request and acknowledge counters in up to seven external elan devices (or in an external device that implements the elan frame transfer protocol). the request and acknowledge counters are used to indicate the presence of a frame being forwarded and to acknowledge receipt of the frame, respectively. this channel also supports hardware that implements a ring of data descriptors that are used for the seven transfer queues (discussed in more detail later). dma controller operations performed by the receive channel take place largely autonomously (after initial setup); the receive channel simply notifies the switch processor upon the completion of reception of each incoming frame, and supplies the necessary frame parameters to the switch processor via hardware registers. however, the remaining channels perform their transfers completely under firmware control by the switch processor. in operation, the switch processor loads the appropriate dma control registers with the desired transfer parameters and then enables the channel. the hardware will then autonomously complete the transfer and notify the switch processor upon completion via an interrupt. address lookup hardware the dma controller contains internal hardware that performs an address lookup on the source and destination mac addresses in the headers of received ethernet frames, and attempts to match them against entries in an address table maintained in external ram. during frame reception, the dma receive channel extracts the 48-bit source and destination mac addresses from every incoming frame. these are then passed through a hashing process that generates a 16-bit hash key ; the key, in turn, is used as an index into a hash array in external ram. the entries in the hash array are expected to point to zero or more hash buckets , with each hash bucket being assigned to a unique mac address. if multiple hash buckets are associated with a single hash array entry, they are concatenated into a linked list, that is searched by the address lookup hardware to locate the correct hash bucket for the given source or destination mac address. (the search is performed by comparing the actual mac address against a 48- bit address field in the hash bucket.) if a match is found for either the source or the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 50 destination mac addresses, or both, the pointers to the appropriate hash buckets are passed to the switch processor along with the received frame. a similar address lookup process is also performed by the transmit channel for a frame that is being read over the pci expansion bus from a remote device. this lookup is restricted to the source mac address only; further, the lookup is only done if required by the switch processor. (this address lookup is used during the address learning process, when it is desired to learn the source mac addresses of frames that are being read over the pci expansion bus.) memory controller external ram is required for packet buffers used to hold received ethernet packets, as well as data structures needed to perform switching and support system management. the external memory may also contain patch or extension code for the on-chip switch processor. the elan 1x100 therefore contains an integral memory controller unit which supports a variety of standard memories without glue logic. the memory controller is capable of addressing a total of 16 megabytes of row/column multiplexed-address memories (i.e. dram), or a total of 4 megabytes of linear-address memories (i.e. sram, eprom and eeprom), in any combination. 1 the address space is divided into four banks, each of which has an independently programmable memory type and access time. this allows a mix of fast and slow devices to be used in the system. programming of eeprom devices is done under control of switch processor microcode. the memory controller is capable of performing up to 1 32-bit transfer every 2 clock cycles (40 nsec at the nominal clock frequency of 50 mhz) to or from an sram bank, for a maximum sustained throughput of 100 mb/s. memory device types or speeds cannot be mixed within a bank (i.e., a bank cannot consist of part eeprom and part sram, for example) without special logic that is outside the scope of this document. in general, memory devices of different types must be assigned to different banks, and selected with different chip selects. the memory types used for standard switching by the pm3351 are summarized in the table below: 1 the reduced space available for the non-multiplexed-address memories arises due to pin limitations: only 18 memory address lines are driven to the pins driving the external memory bus (maddr[17:0]), whereas 20 address lines would actually be required (in conjunction with the four bank selects and the four byte-enables) to span the entire 16 mb address space. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 51 memory type spee (nsec) latency (cycles) peak bandwidth standard sram 15 2 100 mb/s standard eprom/eeprom 150 12 17 mb/s the standard memory types that should be used with the elan 1x100 are 15 nsec sram and 120/150 nsec eprom or eeproma memory ready input pin (mrdy*) is implemented for linear memory devices that have other speed requirements. this pin is sampled by the elan 1x100 when accessing memories in standard asynchronous sram mode; it may be driven inactive, prior to the end of any memory cycle by an external memory timing generator to suitably lengthen the access cycle. the sampling of the mrdy* input takes place at the end of the first clock cycle of a 2-cycle sram access. accesses to banks configured for memory types other than 2-cycle sram cannot be controlled using mrdy*. the mrdy* pin should be tied low (i.e., logically deasserted) if it is not used. the elan 1x100 generates four separate write enables to enable individual bytes within each addressed 32-bit word to be written to independently of the others. this allows the elan 1x100 to perform byte (8-bit), halfword (16-bit), tribyte (24-bit) and fullword (32-bit) memory accesses without using read-modify-write operations. an interrupt input pin (mintr*) is provided for special applications. a ttl logic low level on this pin causes an interrupt to be generated to the internal switch processor, the pci bus (via the int* output), or both. the use of this interrupt input is application dependent and beyond the scope of this datasheet. the mintr* pin should be tied high (i.e. logically deasserted) if it is not to be used. pci expansion port the elan 1x100 includes a pci v2.1 compatible bus master and slave interface, which serves as an expansion port allowing multiple elan 1x100 and/or elan 8x10 chips to be interconnected in the same system to create switches with larger numbers of ports. the expansion port supports a maximum bus clock of 40 mhz (resulting in a >1 gbit/s peak transfer rate and a sustained throughput of 500 mbit/s), and contains several fifos to increase burst throughput and perform clock synchronization. the pci expansion port may be used for either expanding a switch built around elan switch devices (to a maximum of eight pm3351 and pm3350 chips) or to allow the elan 1x100 to be used in special applications requiring an intelligent 100 mb/s ethernet interface. in these applications, the on-chip dma controller uses the pci expansion port master interface to notify other elan switch devices or the host cpu of the presence of packets to be transferred, and to copy packets or data structures under control of the switch processor from external elan switch devices to the local memory pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 52 space via the pci bus. note that data are never transferred directly between the mac channels and the pci bus. the pci bus master interface serves to allow the dma controller as well as the cpu to initiate transactions on the pci bus. the bus master conforms to the requirements of the pci v2.1 specifications for standard transaction initiator devices, and can perform configuration space as well as memory space read and write transfers. (note that the elan 1x100 does not support i/o space transactions.) the pci bus master unit contains a 64-byte write fifo to buffer data being written by the elan 1x100 device to an external target on the pci bus, as well as a 128-byte read fifo to hold data that has been read from an external target. these fifos permit the bus master to operate using long burst transactions for increasing the pci bus bandwidth utilization. the bus master interface also conforms to the pci v2.1 latency timer requirements, and supports back- to-back transfers. the pci slave interface logic within the expansion port block responds to transfer requests from external bus masters, performing the necessary accesses and transferring the requested data. the slave interface logic acts as a responder during frame transfers between devices belonging to the elan chipset, supplying ethernet frame data to requesters as necessary. an external processor can also use the pci slave interface to gain access to internal device registers and data structures in the local memory space, or to download firmware or data to the elan 1x100 switch processor. the slave interface unit contains a 32-byte write fifo and a 128-byte read fifo to improve burst behavior during pci reads and writes: the write fifo buffers data being written to the elan 1x100 by external devices, while the read fifo holds data read from local memory or internal registers in response to pci memory read commands from external requesters. note that the slave interface only responds to configuration space and memory space reads and writes; i/o space reads and writes are not supported. the slave interface conforms to the access latency, access ordering and disconnect rules of the pci v2.1 standard. a set of special registers are provided in the pci configuration space that may be used to alter the access latency rules imposed by the slave logic in order to improve pci bus utilization if required. the expansion port also contains hardware to speed up intercommunication between elan 1x100 and elan 8x10 devices via the pci bus. this hardware takes the form of eigth request counters and eight acknowledge counters. each request/ acknowledge counter pair is dedicated to supporting communications with a specific external elan device. an external elan 1x100 device will increment a request counter to signal that a frame or message data is available to be read, and will increment an acknowledge counter to acknowledge that it (the external elan 1x100) has read a message or frame from the local elan 1x100. standard pci reads and writes can be used to increment the request and acknowledge counters. more details on these counters are supplied below. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 53 the expansion port is compatible with the "pci local bus specification", release 2.1. to support the use of the elan 1x100 in standalone switch system applications, a simple external bus arbiter (easily implemented in a single programmable logic device) must be provided to arbitrate between pci bus accesses of multiple elan devices. the pci bus interface within the expansion port runs synchronously to the pci bus clock, which must be supplied on the pciclk input pin. this clock may range from 25 mhz to 40 mhz, with the duty cycle specified in the pci local bus specification. the elan 1x100 pci bus interface implements synchronization logic to transfer data between the pci bus clock domain and the internal device clock. pci transactions supported the on-chip pci interface is capable of initiating the following commands: memory read memory write configuration read configuration write the on-chip pci interface supports the following pci commands as a target: memory read memory write configuration read configuration write memory read multiple memory read line memory write and invalidate pci vendor id and device number the vendor id assigned to the elan 1x100 device (in the pci configuration register space) is 11f8 hexadecimal, while the device number is 3351 hexadecimal. the class code for the elan 1x100 is set to 0x020000 hexadecimal. slave read prefetching as already mentioned, the pci bus slave logic contains a 128-byte read fifo buffer to speed up reads made from this elan 1x100 device over the pci bus. this fifo has a prefetch capability that is activated when accessing external memory space: it attempts to read ahead and speculatively obtain more data words than have been actually requested by the transaction master, thereby potentially increasing the efficiency of burst transfers. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 54 the prefetch capability functions as follows. initially, the pci slave read fifo is empty, and remains so until the pci slave is idle. when a read transaction is initiated by an external bus master, the pci slave logic will perform a disconnect with retry, after a configurable amount of cycles, because the read fifo is empty and no data can be returned. the slave logic then decodes the target address of the read: if it corresponds to external memory space, then the prefetch capability is activated. the slave logic subsequently requests the memory controller to begin fetching from the target memory address; the data returned are placed into the slave read fifo, and the pci slave logic continues to fetch additional data words at consecutive addresses until the slave read fifo is full. up to 128 bytes of data may be fetched in this way and placed into the slave read fifo. at some point, the original pci transaction initiator (bus master) is expected to retry the access. (according to the rules of the pci bus, it is an error for the bus master to abandon an access that has been terminated with a disconnect-and-retry.) the pci slave logic will compare the address being requested by the pci bus master for the retried transaction to the address from which it began the prefetch; if a match occurs, the slave logic will return the data present in the read fifo in a continuous burst of back-to-back data phases on the pci bus. the burst of transfers on the pci bus will continue as long as (1) the read fifo is not empty and (2) the bus master does not terminate the access. if the read fifo empties during a transfer (possibly because the memory controller cannot satisfy the requests from the pci slave logic at a sufficient rate), the pci slave logic will issue another disconnect with retry, and continue to request the memory controller for more data. the bus master is again expected to retry the access, and the cycle continues. if the bus master terminates the access in any way, the pci slave logic will stop placing data on the pci bus and flush the read fifo to discard any remaining unread data words. it will then proceed to fulfill the next pci read or write access. the use of the pci slave read fifo enhances the ability of the pci slave logic to maintain the utilization of the pci bus by transferring data in long bursts. if sufficient delay is inserted by the bus master between the initial disconnected access and the subsequent retry, the pci slave will have time to read ahead by a substantial number of words (up to 32) and can therefore transfer data in a long burst when the bus master finally retries the access. to further improve the efficiency of the pci slave interface, the slave logic has the capability of latching and holding up to two different target read addresses from two different bus masters at a time. this allows the first bus master to make a read access, which will be disconnected with retry by the pci slave logic after the target address has been latched; another bus master can then make another read access at a different address, which will also be disconnected with retry by the slave logic after the address pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 55 has been latched. (only two such addresses can be latched by the slave; if yet a third master makes another read access to another address, the slave logic will also disconnect this master with a retry, but will not latch the address internally.) the availability of the second read address means that the pci slave logic can begin immediately fetching data from the second location into the read fifo after the first bus master terminates its access, without waiting for the second bus master to retry the access, and hence the pci slave logic can improve its utilization of the available memory and pci bus bandwidth. note that writes are not allowed to be completed out-of-sequence with reads, and vice versa. watchdog timer facility the elan 1x100 device incorporates a simple internal watchdog timer that optionally initiates an automatic system hardware reset if some catastrophic error occurs that causes the switch processor to lock up or enter an undefined state. the watchdog timer is built around the 16-bit wtimer device control register (described in more detail in a later section). the wtimer register principally acts as a down-counter, decrementing its value by 1 every millisecond until it reaches zero. firmware running on the switch processor will, under normal circumstances, periodically reload the wtimer register with a non-zero value before it reaches zero. if however, the switch processor firmware encounters some serious system fault that prevents it from reloading the wtimer register before it has counted down to zero, the watchdog facility will assert the erst* output low for one millisecond. if the erst* output is tied to the system reset line (this is made possible by the fact that erst* is an open-drain output), then the watchdog timer facility will effectively reset the entire system. alternatively, the erst* output can tied to a resistive pull-up and simply monitored by an external system processor; a hardware or software reset of the elan 1x100 device should be performed if the erst* output goes low (logically asserted). the value used by the switch processor firmware to reload the wtimer register is a configurable parameter, and should be chosen to ensure that false system resets do not occur under high loads without simultaneously incurring an excessive system recovery time. the maximum reload interval is approximately 65 seconds; the minimum interval is about 2 milliseconds. a value of 1-2 seconds is recommended. if the wtimer register is loaded with all-ones (0xffff hex) the watchdog timer fac ility will be disabled, and the wtimer register will be prevented from counting down and asserting the erst* output. (the watchdog facility can hence be disabled by the system implementer by setting the configurable reload value to 0xffff hex.) note that the wtimer register rolls over to 0xffff after it has counted down to zero, thereby automatically disabling itself after the 1 millisecond reset duration is over. if the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 56 wtimer register is left untouched by the initialization process, then it will default to a disabled state, i.e., it will remain loaded with 0x ffff and, as a result, w ill not count down. if the switch processor itself detects an unrecoverable fault that requires a general system reset, then the switch processor firmware will write a value of zero to the wtimer register under program control. this will cause the erst* pin to be immediately asserted (driven low), potentially causing a hardware reset or notifying the system processor that a fault has occurred. device configuration basic device and system configuration (i.e., memory types and speeds for various banks, the pci base address for this elan 1x100 device, and auto-boot and master/slave enable flags) are supplied by means of resistor pull-ups and pull-downs connected to the 32-bit data bus. this configuration information is latched into internal registers upon the second sysclk rising edge after the rst* input to the elan 1x100 transitions high, and sets up the elan 1x100 internal hardware. the 32 bits of configuration data presented on the memory data bus are latched into the 16-bit dconfig and mconfig registers internal to the elan 1x100; these registers may also be accessed by the switch processor and by external devices via the pci bus. as an alternative to resistor pull-ups and pull-downs, a tristate buffer or tristatable register may be used to drive configuration information on to the data bus during reset. care should be taken to remove the data by tristating the buffer or register no earlier than 2 sysclk periods after the trailing edge of the rst* input, and no later than 10 sysclk periods after the latter (to prevent memory data bus contention). the memory data bus is mapped to configuration bits as follows: device pin register bit description mdata[31] pcirun this input selects the default operating mode of the pci interface. if logic 1: ? the on-chip pci interface latches its slave memory base address from the chipid configuration bits (mdata[25:22]). ? the pci command register bits for "bus master" and "memory space" are set (1), thereby allowing the device to respond to pci memory space accesses and to be a bus master. if logic 0 ? the pci interface has a memory base address of 0. ? the pci command register bits for "bus master" and "memory space" are cleared (0); the device is disabled from responding to pci memory space accesses and will not be a bus master. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 57 mdata[30] riscrun a low on this signal halts the switch processor upon reset, effectively placing the device into stand-by mode. mdata[29] rsttm for test purposes only. pull low for correct operation. mdata[28] imdis internal memory disable: if high, the internal switch processor rom is disabled at initialization time. mdata[27] pci3v if high, configures the pci interface for the 3.3v signaling environment. if low, configures the pci interface for the 5v signaling environment. must be set to logic 0 since all ac parametric testing done with the 5v signaling conditions. mdata[26] firm reserved for use by switch processor firmware. mdata[25:22] chipid[3:0] these bits determine the pci memory base address at initialization time if the pcirun configuration bit is high. in this case, the chipid[3:0] inputs are zero-extended to 8 bits and loaded into the most significant byte of the memory base address register in the pci configuration register space. mdata[21:16] rtcdiv[5:0] real time clock divider: selects the divide ratio used for the internal real-time clock prescaler. this field must be set numerically equal to the frequency, in megahertz, of the clock supplied on the sysclk input. mdata[15:14] mxsel[1:0] error! no index entries found. mxsel 00 01 10 11 column address bits 8 9 10 11 dram configurations supported 64k x n & 128k x n 256k x n & 512k x n 1024k x n & 2048k x n 4 meg x n & 8 meg x n mdata[13] mslo the mslo bit extends read and write cycles to accommodate slower dram devices in local memory devices. if mslo is high, 80ns dram is expected. if mslo is low, 60ns dram is expected. (mslo must be a logic 0 if edo dram is used with the pm3351 since the device is intended to work with 60 ns dram; as previously stated, dram, if used, is intended for non- switching applications). mdata[12] mdcas this bit identifies the type of dram connected to the memory interface. if mdcas is high, the memory interface will generate control signals for 2-cas drams; otherwise, it generates signals for single cas drams. (again, as dram is generally not used for standard switching, these bits will usually be dont- cares). mdata[11:9] mtype3[2:0] indicates the type of memory connected to the mcs[3]* output: mtype3[2:0] 000 001 010 011 100 101 110 111 selected memory type reserved reserved 15ns sram reserved reserved 150ns (e)eprom 60ns edo dram reserved pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 58 mdata[8:6] mtype2[2:0] indicates the memory type associated with mcs[2]*. the encoding is the same as for mtype3[2:0]. mdata[5:3] mtype1[2:0] indicates the memory type associated with mcs[1]*. the encoding is the same as for mtype3[2:0]. mdata[2:0] mtype0[2:0] indicates the memory type associated with mcs[0]*. the encoding is the same as for mtype3[2:0]. after the hardware configuration information has been latched from the data bus, it is loaded into the dconfig and mconfig registers. the lower 16 bits of the configuration word (i.e., bits 0 through 15, latched from mdata[15:0]) are loaded into the mconfig register, with mdata[0] being loaded into the lsb of mconfig. the upper 16 bits (i.e., corresponding to mdata[31:16]) are loaded into the dconfig register in a similar fashion. system bootstrap image the elan 1x100 is designed to self-initialize upon power-up, using information and operating firmware supplied as a pre-determined image (referred to as the boot image ) in external memory (typically, eprom or eeprom). the boot image may be located anywhere in the 16 mb address space, and it must start on a 64 kb boundary . the elan 1x100 expects the boot image to be formatted in a predefined manner, as described below. the boot image consists of a boot header and a set of boot data blocks. boot header the boot image is distinguished by a special 32-bit signature followed by a predefined configuration header. the elan 1x100 will, therefore, perform some basic initialization indicated by the hardware configuration word loaded from the data bus after reset, and then begin scanning the entire memory space at 64 kb boundaries for the boot image signature. it expects to find the four bytes of the signature aligned on four consecutive 32-bit boundaries, as indicated in the following table: offset from 64kb boundary expected contents (hex) +0 xxxxxxc7 +4 xxxxxxa8 +8 xxxxxx37 +12 xxxxxx59 the use of a signature to locate the boot image, rather than an explicit address, implies that it is not necessary to indicate the exact location of the configuration image to the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 59 elan 1x100. instead, the boot image may be located anywhere throughout the 16 mb address space. in addition, a boot image need not even be supplied using an eprom or eeprom; it may also be downloaded to ram by an external device or host processor. the elan 1x100 expects to find executable firmware code within the boot image that will perform the actual initialization process. however, the boot image is generally only 8 bits wide, and thus the firmware code supplied within it cannot be directly executed by the elan 1x100 switch processor, which uses 32-bit instructions located on 32-bit boundaries. it is thus necessary for the elan 1x100 to copy the boot image to a block of ram that is set aside for the purpose, and to convert the 8-bit boot image to a 32-bit version so that the boot firmware code can be directly executed. when a proper boot image signature is found, therefore, the elan 1x100 will automatically go on to read a preformatted header within the boot image. this header should supply information required to copy the boot image to a pre-allocated block of ram, and is formatted as follows: field size, bytes byte offsets from start mnemonic description 1 +16 hdrflags boot image processing flags 3 +20,+24,+28 cpytarget target ram block to copy 8-bit boot image to 2 +32,+36 cpysize amount of data to copy in 64- byte blocks 3 +40,+44,+48 cpyfrom source of copy data within boot image 3 +52,+56,+60 bootstart address to begin execution at after copy is complete 4 +64,+68,+72,+76 checksum 32-bit checksum, computed over entire boot image (including checksum field) 4 +80,+84,+88,+92 spacer must be set to 0x00000000 hexadecimal the hdrflags field supplies some control bits that determine how the elan 1x100 will handle the boot image, and is formatted as follows: 7654 0 eightbit cpyint jmpint reserved eightbit: if set, indicates that the boot image is formatted as an eight-bit-wide memory pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 60 block; otherwise, indicates a 32-bit boot image in memory. if this bit is not set (indicating a 32-bit-wide boot image), the cpyint and jmpint flags must also be cleared. cpyint: if this bit is set, the contents of the boot image should be copied to the internal instruction ram of the switch processor rather than a block of external memory. this bit should be set only if the eightbit flag is also set (i.e., for a standard 8-bit-wide boot image). as a 32-bit-wide boot image, can be executed directly, no copy is done, internal or otherwise. jmpint: the jmpint bit signifies, if set, that the bootstart address indicates an address present in the instruction ram of the switch processor, rather than an address in a block of external memory. this bit should be set only if the eightbit flag is also set (i.e., for a standard 8-bit-wide boot image). it is assumed that a 32-bit-wide boot image will be executed directly from its external memory location. if the eightbit flag is set, the elan 1x100 will copy data bytes from the eprom or eeprom boot image to consecutive byte addresses in a block of 32-bit wide ram, thereby converting the 8-bit boot image to a 32-bit boot image that can be executed. the target ram may be either external (sram or dram) or the internal instruction ram within the switch processor, according to whether the cpyint flag is set. the cpytarget, cpysize and cpyfrom fields of the header define a block transfer that must be performed from the boot image to an area of external sram or internal instruction ram in order to convert the 8-bit boot image to an executable 32-bit image. after the copy and conversion has been done, the bootstart field denotes a 24-bit address from which the elan 1x100 switch processor will begin executing code, either inside the internal instruction ram (as is generally the case), or external ram. the code at this location is responsible for initializing the elan 1x100 system and environment. the jmpint bit signals whether bootstart refers to internal or external ram. the checksum field contains a 32-bit checksum computed over the entire boot image. the bootstrap firmware will recompute this checksum and compare it with the value in the checksum field. if a mismatch occurs, the elan 1x100 will consider the boot image as invalid, and will terminate the system initialization and startup process and report an error. note that the boot image header above is described as it would appear from the switch processor. in the view from the 8-bit image contained within an eprom or eeprom, the addresses would be divided by 4. this is because the 8 bit wide memory is connected to the least-significant byte lane of the memory data bus. each byte within pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 61 the eprom or eeprom, therefore, will start on a 32-bit boundary and occupy the least-significant 8 bits of a memory word; the upper 24 bits of the word will be ignored by the elan 1x100. note that this header only uses the least significant byte even if a 32 bit boot memory is being used. an alternative view of the boot header, giving the components of the header as they would appear inside the 8-bit-wide rom, is given below: 0x59 0x37 0xa8 0xc7 0 cpytarget[23:0] hdrflags[7:0] 4 cpyfrom[15:0] cpysize[15:0] 8 bootstart[23:0] cpyfrom[23:16] 12 checksum[31:0] 16 spacer[31:0] 20 typical usage in the standard eprom or eeprom bootstrap image, the hdrflags field is set to 0xe0 hex, indicating an 8-bit-wide boot image that must be copied into the switch processor's internal instruction ram, and then executed. the boot image that is copied into the internal ram includes the normal frame switching firmware, as well as a small bootstrap loader routine. the bootstrap loader (which will be pointed to by bootstart) will then copy the remainder of the 8-bit-wide boot rom into external memory, and finally jump to an entry point in the code copied into external memory that will configure the rest of the device and the system if necessary. a 32-bit-wide boot image must always set the hdrflags field to 0x00, or else the bootstrap process will fail. in this case, the cpytarget, cpysize, and cpyfrom fields are ignored, as no copying is done. it is expected that the bootstart value will be a valid address in the 32-bit-wide memory containing the boot image where execution must begin in order to initialize and start the system. boot data in addition to the signature, header and bootstrap firmware code, the boot image is expected to contain configuration information such as the sizes of memory buffer pools, buffer limits defined on a per-port basis, predetermined mac addresses to be placed in the routing tables, the location of external elan devices, the mac address and ip address assigned to this elan 1x100, and so on. the boot image must also supply the operating firmware that is required by the elan 1x100 for frame switching and management. the general layout of the standard boot image supplied by pmc is shown below (note that the memory addresses increase downwards): pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 62 0 boot image signature boot image header elan 1x100 switching firmware bootstrap loader routine system table elan 8x10 switching firmware boot tag space 32 kbytes boot tag processing code rtos firmware code (optional) udp/ip stack firmware code (optional) 256 kbytes snmp agent/mib firmware code (optional) the bootstrap firmware code performs a brief self-test, testing external memory and verifying the boot image checksum. the status of each stage of the self-test is output as writes of binary codes to the (configurable) memory location at which the optional led register may be located. after the self-test completes, the elan 1x100 uses the information read from the boot image to set up the fixed and dynamic data structures in external and internal ram, and then initiates normal operation. the actual bootstrap firmware is divided into two portions, referred to as the boot tags and the boot tag processing code . the boot tags essentially comprise a set of parameter blocks that define various data structures or hardware entities that must be initialized in a particular way, as well as the data values required for the initialization. the boot tag processing code scans over the array of boot tags; for each class of boot tag, an associated routine is invoked to actually perform the required initialization. this approach permits the initialization process to be extended very simply to cover new types of structures or new hardware features: additional boot tags (together with their associated routines) can be included in order to perform new types of initialization in a well-structured manner, without having to be concerned about interactions between different portions of the bootstrap firmware. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 63 as shown, the basic bootstrap code and the master switch operating firmware occupy 32 kbytes of eprom/eeprom space; if an snmp agent is required (with the associated udp/ip stack and rtos firmware), then the boot image size requirements rise to 256 kbytes. contact the factory for more information on the boot image, and the means of creating one. master/slave system initialization in a multiple-elan 1x100 and elan 8x10 system, a single elan 8x10 or elan 1x100 device may be designated as a master and possess a boot image in an eprom or eeprom. this elan 1x100 is then responsible for initializing and configuring all the other elan 1x100s in the system via the expansion port interface. this is facilitated by the riscrun configuration bit supplied on the memory data buses of all of the elan 1x100s in the system. in this application, the master elan 1x100 should have its riscrun bit pulled high during reset, and all of the other slaves should have the corresponding bits pulled low, ensuring that they enter standby mode the master elan 1x100 can then configure itself, download boot information to the ram interfaced to the remaining elan 1x100s, and finally enable all of the slave elan 1x100s to start running. the slave devices can then initialize themselves using the downloaded information. note that the firmware images for both the elan 1x100 and elan 8x10 devices are present in the boot image. this is done to permit a single boot image (and consequently eprom or eeprom) to be used to initialize an entire system of elan devices of either type. the system table is used for this purpose: it contains information regarding the initialization and operating code requirements of every device in the system, and the bootstrap firmware running on the system master device uses this table to properly initialize and start the slave devices. slave initialization is carried out by the master device after the master has loaded its boot image, set up its private environment, and determined that it is indeed the master; at this time, it copies the bootstrap firmware, the appropriate block of switching firmware (depending on whether the target slave device is an elan 1x100 or an elan 8x10) and the appropriate set of boot tags into the slave device's local ram space across the pci bus. the master then causes the slave to begin executing the bootstrap firmware and initialize itself. once initialization is complete, the slaves notify the master, and the system is ready for frame processing. host-controlled system boot in a host-controlled system, it is expected that all of the elan 1x100 devices are configured as slaves, i.e., they do not possess eproms or eeproms containing boot images that permit them to self-configure at power-up. instead, they enter a halt state after system reset and wait for the host (i.e., system master processor) to download the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 64 required boot image and enable them to begin executing it. this can be done by converting the bootstrap firmware to run on the host system. the bootstrap firmware should then perform the same general functions (reading each boot tag and implementing the required initialization function) to pass the appropriate information to the elan devices. contact the factory for more information and sample code. stand-alone system boot typically an elan 1x100 device will be part of a multiple elan device system, where the master device is responsible for controlling the initialization of the slaves; or work in conjunction with a host processor, in which case the host is required to take over these initialization and start-up functions. however, it is possible for a system to be designed where each elan device has its own eprom or eeprom containing a private boot image, and it is not necessary for a master entity to initialize other devices. in such a system, some elements of the multi-device boot rom are unnecessary; the resulting boot image would be laid out as follows: 0 boot image signature boot image header elan switching firmware bootstrap loader routine boot tag space 32 kbytes boot tag processing code rtos firmware code (optional) udp/ip stack firmware code (optional) 256 kbytes snmp agent/mib firmware code (optional) contact the factory for further information and sample boot images. configuration parameters a number of configuration parameters can be adjusted by the system implementer to create a boot image for various types of target systems. the configuration parameters are located in a single header file that is read automatically whenever a boot image is pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 65 created using the development kit. the following table gives the user-accessible configuration parameters: general system parameters mstrchipnum chip number assigned to master device (generally 0) hashmask mask setting size of hash table array (0x1fff max) numchips total number of elan 1x100 and elan 8x10 devices chipbase0 upper 8 bits of base address of device 0 on pci bus chipbase1 upper 8 bits of base address of device 1 on pci bus chipbase2 upper 8 bits of base address of device 2 on pci bus error! no index entries found. upper 8 bits of base address of device 3 on pci bus chipbase4 upper 8 bits of base address of device 4 on pci bus chipbase5 upper 8 bits of base address of device 5 on pci bus chipbase6 upper 8 bits of base address of device 6 on pci bus chipbase7 upper 8 bits of base address of device 7 on pci bus boot image header parameters boot_start target area reserved for copying boot image from rom boot_entry entry point of bootstrap loader/firmware in copied image boot_size size of boot image in 64-byte blocks (i.e., rom copy size) led_start address of led status register for signaling status codes rom_loc boot image eprom/eeprom base address (copy source) pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 66 parameters specific to elan 1x100 bigstructst start of pool of free packet buffers nbigstructs number of free packet buffers in pool hashstructst start of pool of free hash bucket structures nhashstructs number of free hash bucket structures in pool smallstructst start of pool of free forwarding tag structures nsmallstructs number of free forwarding tags in pool dispstructst start of pool of free data descriptor structures for messages ndispstructs number of free message descriptors in pool ddringst start of transfer ring structures nddsperring number of elements per transfer ring nddsperringshift log 2 of number of elements per transfer ring parameters specific to elan 8x10 xpd_dd address of first data descriptor attached to transfer queues freehb start of pool of free hash bucket structures freepb start of pool of free packet buffer structures freedd start of pool of free data descriptor structures num_freepbs number of free hash bucket structures in pool lclpblim buffer limit per port note that further information on elan 1x100 data structures can be found later in this document. self test and error reporting the bootstrap firmware code is expected to implement any required power-on self-test (post) functions that are required by the system of which the elan 1x100 is a part. if any of the post routines detects an error, it is expected to halt the bootstrap process and write a special code to the (optional) led register that is mapped into the elan 1x100 memory address space. if the led register is implemented, then the failure indication can be obtained for diagnostic purposes. currently, two primary types of self-test routines are implemented: 1. a checksum is computed over the complete boot image and compared to the precomputed checksum in the boot image header. if a mismatch is detected, then the boot image is considered to be corrupted, and cannot be used for system initialization. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 67 2. a destructive ram test is performed over the entire ram space with the exception of the space occupied by the boot image itself. the ram test is quite simple, and consists of writing a known pseudorandom value to each location in the ram and then reading the data back. if the data read is not equal to that written, then the ram is considered to be defective, and the system cannot begin operation. (the ram self-test is not intended to be an exhaustive device test aimed at unconditionally detecting a faulty ram, but merely a fast and simple test for a gross go/no-go check.) additional self-test routines will be implemented in the bootstrap firmware code as developed. in addition to the self-test functions performed upon system start-up, the elan 1x100 operating firmware also performs numerous checks of its internal state during normal system operation. if an unrecoverable error is detected, the elan 1x100 will output a status code to the led register, and then attempt to restart itself (and possibly the entire system) via the internal watchdog reset facility. if the internal watchdog reset output (as driven onto the erst* pin) is connected to the global system reset, then the elan 1x100 will reset the entire system; otherwise, the erst* pin should be monitored by an external system master to determine when the elan 1x100 is halted due to some fatal error, and must be reset in order to continue. in general, leds 6 and 7 (i.e., the most significant bits of the led register) are intended to be used to provide a general failure indication; led 5 indicates whether the failure occurred at self-test and initialization time, or whether the failure occurred during normal operation; and the rest of the leds supply a diagnostic code that can be used to identify the cause of the failure. the leds also serve to output special codes during system initialization and during normal operation. in this case, leds 6 and 7 will not be lighted. led 5 indicates whether the status pertains to system initialization or normal operation. codes output during system initialization indicate the index of the bootstrap tag being processed during the initialization process, and range from 0 to the maximum number of bootstrap tags in the boot image. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 68 the codes written out to the led register are defined below: description led7 led6 led5 led4 led3 led2 led1 led0 bootstrap tag index off off off tag[4] tag[3] tag[2] tag[1] tag[0] operational status indication off off on info[4] info[3] info[2] info[1] info[0] boot checksum failure blinking on off off off off off on ram self-test failure blinking on off off off off on off operational failure blinking on on code[4] code[3] code[2] code[1] code[0] if a failure is detected at any time that causes the elan 1x100 to halt normal operation, the most significant led (connected to bit 7 of the led register) will be made to blink on and off at a 0.5 second rate. the next-most-significant led (i.e., bit 6 of the led register) will be turned on by writing a zero to this bit position of the led register; this serves as a global failure indication, and may alternatively be polled by system hardware to determine whether a failure has occurred. led number 5 indicates whether the failure occurred during system boot-up or normal operation: if it is lit, the system encountered an unrecoverable error during operation. the remaining five leds are used to signal an error-specific code that can be used for diagnostic purposes. the codes signalling tag processing information, operational information and operational errors during operation are tbd. data structures it is assumed that an earlier bootstrap initialization and configuration phase will have set up some predefined data structures in elan 1x100 local memory. these are the switch processor operating environment (stacks, memory pool, local variables, etc.), transfer rings, free pools (containing packet buffers, data descriptors for messages, hash buckets and forwarding tags), the port descriptor table (with the associated per-port section of the management information base), the mac address hash table (which also contains the per-host section of the management information base), and data associated with the ieee 802.1d spanning tree bridge configuration algorithm. the data structures, their function, and the operations performed on them are described below. in addition, the memory requirements for each type of structure, as well as the general memory map expected by the switch processor operating firmware, are provided in this section. the general layout of the various data structures in ram is shown below. note that addresses increase downwards. the actual addresses delimiting various regions of memory are implementation-specific, and not provided here; instead, the names of the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 69 parameters supplied during the generation of a boot image that control these addresses is given next to the memory regions. a description of how these addresses may be computed, as well as a sample memory map for a typical system configuration, is provided later in this section. 0x000000 switch processor operating environment bigstructst packet buffers ddringst transfer rings dispstructst message data descriptors hashstructst hash buckets smallstructst forwarding tags boot_start boot image copy area top of ram switch processor operating environment the switch processor requires a small operating environment (i.e., data structures and variables) for performing basic frame switching functions. this environment is set up in the external ram during the bootstrap initialization and configuration phase. the entire operating environment occupies about 43 kbytes of space, and must be located starting at address 0x000000 hex in the external memory. the operating environment excludes the space used by ethernet frame buffers and the queueing structures used to track them, and also does not include the code, data or stack spaces that are needed by the (optional) rtos, udp/ip stack, or snmp agent firmware. the general layout of the operating environment is as follows: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 70 0x000000 reserved for switching firmware 0x001fff 0x002000 frequently used variables and parameters (cached) 0x00207f 0x002080 save space for switching firmware (cached) 0x0020bf 0x0020c0 local port descriptor (cached) 0x0020ff 0x002100 background queues (cached) 0x0021ff 0x002200 random number generator table (cached) 0x0022ff 0x002300 expansion port descriptors (cached) 0x0023ff 0x002400 dispatch table 0x0024ff 0x002500 miscellaneous variables and tables 0x0025ff 0x002600 port descriptor error counters 0x00267f 0x002680 transmit distribution fifo 0x0028ff 0x002900 hash table 0x00a8ff pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 71 the components of the operating environment are as follows: 1. the first 8192 bytes of space are reserved for holding switching firmware code. this space is intended to serve as a backup for the internal 8192 byte instruction ram present in the elan 1x100. 2. the next 128 bytes are used to hold various frequently referenced, global variables, such as the exception masks, broadcast counters, etc. these variables normally reside in the switch processor data cache, and hence their memory image may be inconsistent until the cache is flushed to memory. 3. a block of 64 bytes is reserved for use by the switching firmware as a register save space during interrupts. this area is also cached. 4. a local port descriptor is placed in the next 64 bytes. the local port descriptor also resides in the switch processor data cache, and this region of memory will thus contain out-of-date values until the data cache is flushed. the local port descriptor contains statistics and control information used during frame switching, and is described in further detail below. 5. a set of 16 background queues are placed in the next 256 bytes. these queues are used to transfer frames and messages from the foreground switching tasks to background and management tasks. the background queues reside in the cached memory area. 6. the next 256 bytes are reserved for the random number generation table. this table contains an array of seed values that are used to generate pseudo- random numbers during the computation of backoff timer values for half-duplex collision handling. 7. a set of eight expansion port descriptors occupies another 256 bytes. these data structures hold information pertaining to the devices accessible via the pci expansion bus. as in the case of the local port descriptors, the expansion port descriptors are normally cached and the memory region will not be updated until a data cache flush. the expansion port descriptors are discussed in more detail below. 8. a dispatch table, consisting of an array of pointers to firmware routines that acta as handlers for special situations or for error recovery purposes. a block of 256 bytes is reserved for the dispatch table. note that the dispatch table is located immediately following the cached region of the switch processor operating environment; this and all subsequent data structures are not cached. 9. the next 256 bytes are reserved for miscellaneous variables utilized on an infrequent basis by the switching firmware. this includes things such as a generic hash bucket structure and debug variables. 10. a port descriptor error counter structure is provided to hold error and collision statistics for the local (mac) port. the counter block requires 96 bytes of pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 72 storage; the remaining 32 bytes being reserved for future applications. these counters are also described in more detail below. 11. the next 640 bytes are used for a firmware-maintained transmit distribution fifo. this fifo holds flags and address table information for frames that are queued for transmit in the internal 2048-byte transmit fifo, and is used by the switch processor for post-transmit processing. 12. the remaining 32768 bytes of space are reserved for the hash pointer array. this array forms the base of the mac address hash table; each 4-byte entry in the array contains a pointer to a chain of hash buckets that hold the actual per- mac information required for frame switching. the entire array is cleared to zero (null) during the initialization process. the hash pointer array contains a total of 8192 pointers. the first 1024 bytes of the operating environment (ranging from 0x2000 through 0x23ff hex, in the memory map above) are normally cached by the switch processor in the data cache. as the data cache uses a write-back policy, the actual memory locations corresponding to the cached structures may be out-of-date (i.e., not reflect the most recent information written to the locations by the firmware). for instance, the per-port snmp counters contained within the local port descriptors are cached, and hence the memory images of the per-port counters may not be up-to-date. thus the switch processor must be forced to flush the data cache to update the external memory locations prior to reading them from an external cpu via the pci bus. this can be accomplished via the messaging interface described further within this section. it is the responsibility of the bootstrap and initialization firmware contained within the boot image to set up and initialize the entire operating environment described above. variables and tables in operating environment the switch processor operating environment contains a number of variables and tables used during normal operation. some of these memory locations (i.e., those located between addresses 0x2000 and 0x20c0 hex in the memory map above) are normally expected to be cached in the switch processor data cache, while the remainder are never loaded into the data cache by the operating firmware. the following is a brief listing of the significant variables in the operating environment: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 73 variable name width (bits) description cdhstruct 24 pointer to head of linked-list of free hash buckets cdsstruct 24 pointer to head of linked-list of forwarding tags cddfifowr 24 pointer to head entry in distribution fifo error! no index entries found. error! no index entries found. error! no index entries found. cdtotcollide 32 total number of collisions encountered on mac port cddstruct 24 pointer to head of free data descriptor pool reserved for holding messages cdcurrentxpd 24 temporary storage: holds address of expansion port descriptor currently in use cdlnr 32 temporary save space for lnr register in switch processor cdfirsthash 24 temporary storage: holds the address of the first hash bucket or forwarding tag in a chain of address table entries cdhashidxmask 16 bitmask used to restrict the range of the hash key computed as an index into the hash array cdrefmask 16 global bitmask restricting devices and ports to which multicasts and broadcasts may be directed * 8 lsbs are unused, set to zero * 8 msbs correspond to the eight possible devices in a system cdchipnum 8 logical chip number assigned to this elan 1x100 cdnumchips 8 total number of elan chips in system (both elan 1x100 and others) cdpcirefcount 8 reference count to use during broadcasts cdagetick 8 aging task trigger flag cdageenable 8 aging task enable flag cdddsinringshift 16 log 2 of number of elements in each transfer ring structure cdfpulltl 24 pointer to tail of management frame being extracted from internal transmit fifo by firmware cdfpullhd 24 pointer to head of management frame being extracted from internal transmit fifo by firmware cdfpullbytes 16 number of bytes remaining for management frame being read out of internal transmit fifo by firmware cddispatchpci 24 pointer to next free message data descriptor to use for queueing messages for background processing cdfpush 24 pointer to management frame being written into internal transmit fifo by firmware pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 74 packet buffers ethernet frames are stored in the external sram by the elan 1x100 chip in small, fixed length packet buffers ; with multiple packet buffers being chained in a linked list to hold a complete ethernet frame. the size of every packet buffers is determined at configuration time, and may range from 64 to 240 bytes; the default is 80 bytes. each packet buffer contains an 8-byte header holding various control information fields, and from 0 to at most (n - 8) bytes of payload comprising ethernet frame data. (in this context 'n' denotes the total size of each packet buffer: the default 80-byte packet buffers will contain at most 72 bytes of payload.) the ethernet data stored in the packet buffers includes the ethernet header and crc fields. a mac channel byte-swap control bit is implemented in the lwctrl device control register (see register descriptions below). if the byte swap control is set to the default of zero, indicating no byte swap, the packet buffers have the following format (where 'n' is the total size of the packet buffer in bytes): 31 24 23 16 15 8 7 0 byte offset size nextpb 0 last size refcount unused, reserved 4 payloadbyte0 payloadbyte1 payloadbyte2 payloadbyte3 8 payloadbyte4 payloadbyte5 payloadbyte6 payloadbyte7 12 . . . . payloadbyte(n-4) payloadbyte(n-3) payloadbyte(n-2) payloadbyte(n-1) (n-4) if the mac channel is set up to swap the incoming frame bytes, then the payload field of the packet buffers will be byte-swapped, but the headers will be left unchanged, as shown below: 31 24 23 16 15 8 7 0 byte offset size nextpb 0 lastsize refcount unused, reserved 4 payloadbyte3 payloadbyte2 payloadbyte1 payloadbyte0 8 payloadbyte7 payloadbyte6 payloadbyte5 payloadbyte4 12 . . . . payloadbyte(n-1) payloadbyte(n-2) payloadbyte(n-3) payloadbyte(n-4) (n-4) pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 75 nextpb: 24-bit pointer to next packet buffer in linked-list of packet buffers constituting a frame. if no next packet buffer exists (i.e., this is the tail of the linked-list), then this field is null (all-zeros). size: 8-bit size of packet buffer payload (excludes the 8-byte header), in bytes. refcount: 8-bit reference count associated with frame: gives the number of data descriptor ring queues that are pointing to this packet buffer. lastsize: 8-bit count of total number of valid payload bytes (not including the 8-byte header) in the last packet buffer in the linked-list of buffers. only valid if this is the first packet buffer in the linked-list, and there is more than one packet buffer in the linked-list. payloadbyte0 - payloadbyte(n-4): 8-bit packet buffer payload bytes: contains ethernet frame data for the frame contained within the linked-list of packet buffers. the nextpb field in the packet buffer header contains a pointer to the next packet buffer in a the chain of buffers that holds the entire ethernet frame. if this is the last (or only) buffer in the chain, then this field is set to zero to indicate a null pointer and hence the end of the linked list. the size field holds the number of valid payload bytes (i.e., excluding the 8 packet buffer header bytes) in the packet buffer payload field; for an 80-byte packet buffer, the value in this byte can range between 0 and 72. a value of zero indicates a completely empty packet buffer with no data, which will simply be skipped over by the hardware or firmware with no ill effects. the refcount field holds a reference count indicating the number of ports or devices to which the packet buffer contents must be transmitted, and is used to determine when the packet buffer may be freed. the reference count is normally 1 for unicast frames, and equals the sum of the number of destination ports and devices for broadcasts; it is only valid for the last packet buffer in a chain (i.e., when the next packet buffer pointer is null), and is ignored in other buffers. the lastsize field in the header holds the total number of valid bytes, not including the header, in the last packet buffer in a linked list of buffers. it should be placed in the first packet buffer in the chain, and is principally used to optimize processing of packet buffers by the hardware. this field is ignored if there is only one packet buffer in the chain, or if the buffer under consideration is not the first one in the chain. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 76 the remaining bytes in the packet buffer contain the payload, consisting of ethernet frame bytes received by the mac channel of the elan 1x100 (or created via software). the bytes are placed into the packet buffer in the order depicted above, depending on the setting of the byte swap hardware configuration bit. note that 'payloadbyte0' in the above diagrams refers to the first byte received from the medium for the payload of the given packet buffer; in the case of the first packet buffer in a chain, this byte will contain the lsb of the 48-bit mac destination address in the ethernet frame header. packet buffer chains may also be used by the various chips in the system to contain message data that is to be exchanged between devices interfaced to the pci bus. if a packet buffer holds message data rather than ethernet frame data, then the format of the header is unchanged, but the payload field is formatted in a message-specific manner. data contained within packet buffers is never cached by the switch processor, and hence the contents of any packet buffer may be read at any time via the pci expansion port. in normal operation, packet buffers are primarily manipulated by the dma hardware; the switch processor usually writes only the refcount and lastsize fields. data descriptors ethernet frames, messages and other pieces of data being transferred between devices within an elan 1x100 system, or between tasks on a single elan 1x100, are tracked by means of 16-byte data descriptors . (when a data descriptor refers to an ethernet frame that contains management data to be processed by the elan 1x100 system itself, or to buffers holding control and status data that are exchanged for messaging purposes within the elan 1x100 system, then it is sometimes referred to as a message descriptor .) data descriptors form the primary queueing elements in the elan 1x100 device: in addition to forming the individual elements of transfer rings (see below), they are used to hold message information and to create special frame handling queues for management functions. all data descriptors have the same general format, and contain pointers to the first and last packet buffer of a packet buffer chain holding an ethernet frame or a control/status message, flags fields that indicate the processing to be performed on the frame or message, and other information required for processing the payload. in general, data descriptors are formatted as follows: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 77 31 24 23 16 15 8 7 0 byte offset flags nextdd 0 numpbs firstpb 4 srcport lastpb 8 srcchip hashbkt 12 nextdd: 24-bit pointer to next data descriptor in linked-list of data descriptors forming message queue or transfer ring. flags: 8-bit data descriptor flags field, formatted as below. firstpb: 24-bit pointer to first packet buffer in linked-list of packet buffers containing frame or message data. if null (zero), no packet buffer chain exists for this data descriptor; this is only valid for special message data descriptors where all message data can be contained within the 16-byte descriptor structure itself. numpbs: 8-bit count of packet buffers in chain pointed to by firstpb. if firstpb is null (zero), then this field can be used for message-specific purposes. lastpb: 24-bit pointer to last packet buffer in linked-list of packet buffers pointed to by firstpb. if firstpb is null (zero), then this field can be used for message- specific purposes. srcport: 8-bit source port index within device: indicates the mac channel upon which the frame was received. for the elan 1x100, this field wil be 0 since the device only has one port. only valid if the descriptor points to an ethernet frame that was actually received on a mac channel; otherwise, can be used for message-specific purposes. hashbkt: 24-bit pointer to source or destination hash bucket. only valid for ethernet frames; if the descriptor indicates a message, then this field can be used for message-specific purposes. srcchip: 8-bit index of source device that received frame. for the elan 1x100 system, pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 78 this must range from 0 through 7. only valid for ethernet frames; if the descriptor indicates a message, then this field can be used for message- specific purposes. the nextdd field in the data descriptor contains a pointer to the next data descriptor in a chain of descriptors that constitutes a queue of ethernet frames or messages. if this is the last (or only) element in the queue or chain, then this field is set to zero to indicate a null pointer and hence the end of the linked-list. the flags field holds a set of flag bits and bitfields that provide type and control information for the data descriptor, and is formatted as follows: 765 43 0 learn special type msgcode learn: if set, indicates that the source address (sa) field of the ethernet frame pointed to by this descriptor contains a new mac address that must be learned by the device. only valid for ethernet frames received by the elan 1x100 from the pci expansion port; should not be set if the data descriptor points to a message. special: if set, indicates that the data contained within the packet buffer chain pointed to by this data descriptor requires special processing by the firmware, and should not be treated as a normal ethernet frame. this bit is typically set to indicate a message that is being passed between devices on the pci expansion port, or between firmware tasks on an elan 1x100. type: this 2-bit field contains the type of frame pointed to by the data descriptor firstpb field, and is interpreted as follows: type interpretation 00 unicast frame from remote device 01 unicast frame from local mac channel 10 broadcast frame from remote device 11 broadcast frame from local mac channel the above definitions of the type field are only valid if the special bit is clear, indicating that this data descriptor points to a normal ethernet frame. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 79 msgcode: the 4-bit msgcode field is only valid if the special bit is set; in this case, it is used to carry a message code that identifies the type of message carried by the packet buffers to which this data descriptor points. msgcode interpretation 0000 reserved 0001 reserved 0010 reserved 0011 reserved 0100 topology change notification message 0101 forwarding tag deletion request message 0110 reserved 0111 arp broadcast frame message 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved the firstpb and lastpb fields contain the 24-bit addresses of the head and tail, respectively, of the linked-list of packet buffers that are associated with this data descriptor. if only one packet buffer is present in the linked-list, then the firstpb and lastpb pointers contain the same value. it is an error for the firstpb field to be zero in any valid data descriptor that points to an ethernet frame; however, message data descriptors (i.e., those used for exchanging messages between elan 1x100 devices) may optionally have the firstpb field set to zero, if the entire content of the message can be placed in unused fields of the data descriptor. the numpbs field contains the count of the number of packet buffers contained within the linked-list of packet buffers, and may range between 1 and 255. the srcport and srcchip fields indicate the source port index and the source device index, respectively, on which the ethernet frame entered the system. the value in the srcport field will be always be a constant 0 as the elan 1x100 only has one mac channel; the value placed in the srcchip field by any elan 1x100 device is assigned as a system parameter during the device boot-up and initialization process, using data obtained from the boot image. if the learn bit is set in the data descriptor flags field, pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 80 then both of these fields are used to associate the source mac address within the ethernet frame with a particular device and physical port. these fields are generally not valid for message descriptors, in which case they contain message-specific information. the hashbkt field holds the 24-bit local memory address of the address hash bucket associated with either the source or destination mac address in the ethernet frame header. if the ethernet frame is to be broadcast (or the learn bit is set, and the frame must be flooded), the hashbkt field holds the memory address of the hash bucket corresponding to the source mac address in the source device's address space; if, on the other hand, the frame is a unicast, then the hashbkt field contains the memory address of the hash bucket for the destination mac address in the destination device's address space. the hashbkt field has a dual purpose: it is used to learn the memory address of a source hash bucket during broadcasts and floods, and is also used to indicate a target destination hash bucket to use in switching unicast frames once address learning is complete. more details on the use of the hashbkt field in various situations will be provided in subsequent sections. note that the hashbkt field is not used when the data descriptor does not point to an ethernet frame (i.e., is a message descriptor); in this case, it contains message-specific information. data descriptors are never cached by the switch processor, and hence the contents of any data descriptor that is not actually being processed by the switch processor or ring hardware may be read at any time via the pci expansion port. transfer rings a set of fixed-size data structures, called transfer rings , are used to control the transfer of ethernet frames and control/status messages to other devices interfaced to the elan 1x100 via the pci expansion bus. each transfer ring is dedicated to a particular external device, and points to frame or message data that must be sequentially transferred to that device across the pci bus. transfer rings thus operate under a fifo queueing discipline. the general structure of the transfer rings is given below: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 81 ddringst element 0 element 1 element 2 transfer ring 0 element 3 . . element (n-1) ddringst + 16*n element 0 element 1 element 2 transfer ring 1 element 3 . . element (n-1) ddringst + 32*n . . . . ddringst + 112*n element 0 element 1 element 2 transfer ring 7 element 3 . . element (n-1) each transfer ring consists of n elements, where n is a power of 2. (the actual value of n is an implementation parameter, and is determined at system initialization time by configuration parameters in the boot image.) each element in a transfer ring is formatted as a data descriptor structure; the nextdd field in each data descriptor is set up by the bootstrap firmware to point to the next consecutive element in the same transfer ring, with the last element in a transfer ring being set up to point back to the first. the elements in a given transfer ring therefore create a closed linked-list; if the nextdd pointers are followed starting from any element in the ring, the path followed will eventually return to the starting point. the remainder of the fields in each element (beyond the nextdd pointer) are left uninitialized at system startup. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 82 when an ethernet frame or a control/status message is to be transferred to another device in the system, the first free element in the transfer ring corresponding to that device is set up appropriately to point to the frame or message. (if the message is sufficiently small, then the message data may simply be written into fields within the element instead.) additional frames or control messages are queued for the same device by simply setting up consecutive elements in the transfer ring as required; when the last element in a ring has been assigned to a frame or message, the index of the next free element is wrapped back to the start of the ring. the transfer rings are hence used as a true ring buffer. the receiving entity (i.e., external device on the pci bus) is expected to retrieve messages from the appropriate transfer ring when notified to do so. message retrieval is performed in the same order that the messages were placed on the ring. since each element is formatted as a data descriptor structure, the receiving entity can obtain all of the information necessary to retrieve the ethernet frame or control/status message payload by simply reading the contents of the element. after a given element has been read by the receiving entity, it is expected to notify the elan 1x100 that the element is now available to hold another ethernet frame or control/status message. the actual notification process whereby the elan 1x100 signals a remote device that one or more elements contain information about ethernet frames or messages that are ready for transfer is supported by special communication hardware described later. similarly, the notification of retrieved elements by remote devices to the elan 1x100 is also performed with hardware support described in a later section. the elan 1x100 also implements hardware that allows the switch processor to efficiently queue frames and messages to multiple transfer rings, for use during broadcasts and multicasts. note that a unicast message or frame (i.e., information that is directed towards only one external device on the pci expansion bus by the elan 1x100) results in only one data descriptor being allocated and formatted on a single transfer ring. a multicast message or frame, however, requires multiple elements to be set up in as many transfer rings as there are recipients of the message. the sizes of the various transfer rings determine the maximum number of frames or messages that can be queued at any one time for the corresponding devices. the selection of these sizes therefore has a substantial impact on the efficiency and performance of the system. the number of elements within each transfer rign may range from 32 to 65,536, in powers of 2 (representing actual memory sizes of 512 to 1,048,576 bytes). criteria for selecting the sizes of the transfer rings are given later in this section. none of the elements in any transfer ring is cached by the switch processor, and hence they can be read safely at any time over the pci bus. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 83 local port descriptor and port descriptor counters a data structure, called the local port descriptor, is associated with the mac interface within the elan 1x100. the local port descriptor contains various control/status and frame statistics fields, and is updated whenever a frame is received or transmitted by that mac interface. associated with the local port descriptor is another structure, referred to as the port descriptor counter structure , that contains a set of frame error statistics fields which track various error counts updated on an infrequent basis during normal operation. both of these structures are under the sole control of the switch processor, and never modified or read by the rest of the elan 1x100 hardware. both the local port descriptor and the port descriptor counter structure are located in the switch processor operating environment, and are indicated in the previously supplied memory map. note that both structures are completely under the control of the switch processor firmware, and are never read or modified by the elan 1x100 hardware. local port descriptor structure the local port descriptor structure occupies 64 bytes, and is formatted as follows: 31 24 23 16 15 8 7 0 byte offset numcollide reserved 0 0x00 reserved 4 multicastmask maxbuffers 8 portflags reserved backoffmask 12 txframes 16 txoctets 20 txfirstdefer 24 reserved 28 rxucstframes 32 rxvalidoctets 36 rxframes64 40 rxframes65-127 44 rxframes128-255 48 rxframes256-511 52 rxframes512-1023 56 rxframes1024-1518 60 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 84 numcollide: 8-bit count of collisions experienced so far while attempting to transmit the frame at the head of the transmit fifo cleared to zero before starting the first transmission attempt for each frame. note that this field is only used in half- duplex operation. maxbuffers: 16-bit count of packet buffers that remain available to hold incoming received frames; flow control or frame discard will be initiated when this count goes to zero. multicastmask: 16-bit mask used to restrict broadcasts and multicasts received on the elan 1x100 mac channel to a subset of the external devices in the system (that is, to restrict frame forwarding over the pci expansion bus). the lower 8 bits of this mask are always zero. backoffmask: 16-bit mask used to limit the range of collision backoff values generated by the truncated binary exponential backoff algorithm for this port. note that only the lower 10 bits are significant; the upper 6 bits of this field should always be set to zero. portflags: 8-bit control flags used for controlling switching of frames received over the elan 1x100 mac port, or transmitted over the port. txframes: 32-bit count of frames (unicast, multicast or broadcast) successfully transmitted on this port without errors. txoctets: 32-bit count of total number of bytes successfully transmitted on this port without errors. txfirstdefer: 32-bit count of total number of frames that were forced to defer to incoming (receive) traffic during their first transmission attempt. this counter will always be zero if the mac port is configured for full-duplex operation. rxucstframes: 32-bit count of valid unicast frames received on this port. rxvalidoctets: 32-bit count of non-errored bytes received on this port. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 85 rxframes64: 32-bit count of frames received on this port, whether errored or non-errored, that were 64 bytes in size. rxframes65-127: 32-bit count of frames received on this port, whether errored or non-errored, that ranged between 65 and 127 bytes in size, inclusive. rxframes128-255: 32-bit count of frames received on this port, whether errored or non-errored, that ranged between 128 and 255 bytes in size, inclusive. rxframes256-511: 32-bit count of frames received on this port, whether errored or non-errored, that ranged between 256 and 511 bytes in size, inclusive. rxframes512-1023: 32-bit count of frames received on this port, whether errored or non-errored, that ranged between 512 and 1023 bytes in size, inclusive. rxframes1024-1518: 32-bit count of frames received on this port, whether errored or non-errored, that ranged between 1024 and 1518 bytes in size, inclusive. the numcollide field is used to track the number of consecutive collisions encountered when attempting to transmit a given frame in half-duplex mode. it is cleared to zero prior to starting the transmit of every frame. if a collision terminates the frame transmission attempt, this field is incremented by one; if the count of collisions for this frame exceeds the pre-defined maximum (generally, a default value of 16, according to the ieee 802.3 standard), then the frame is discarded and an error is reported. the numcollide field will always be zero if the mac port is in full-duplex mode. maxbuffers is expected to be initialized (during the system boot-up process) with the maximum number of packet buffers that may be allocated to hold ethernet frames by the elan 1x100 during reception. this field is decremented by the number of packet buffers used to store each received ethernet frame; when it becomes less than or equal to zero, the switching firmware will refuse to accept any more frames, and will discard frames if received. maxbuffers is incremented whenever an ethernet frame that was received on this mac port has been completely transferred to all external elan devices over the pci expansion bus, and its packet buffers are freed. if backpressure (for a half-duplex link) or pause flow control (for a full-duplex link) is enabled, then a globally-configurable threshold is defined; if the value of the maxbuffers field falls below this threshold, then the mac channel will start the appropriate flow control mechanism, which will consist of either channel jamming in half-duplex mode, or transmission of a pause control frame to the upstream station in full-duplex mode. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 86 the 16-bit multicastmask field is used to restrict broadcasts, multicasts and floods of packets received on the mac channel with which this local port descriptor is associated. the 8 lsbs of this mask are always set to zero on the elan 1x100, while the upper 8 bits of the mask correspond on a one-to-one basis to the eight possible devices in the system. a device is permitted to be part of a multicast if its corresponding bit in the multicastmask field is set to a '1'. (note that the bit in the multicastmask corresponding to the elan 1x100 device itself is always set to zero at initialization time.) the multicastmask field is logically anded with the global restriction mask managed by the spanning tree protocol entity to permit broadcasts to be further restricted to remove loops in the broadcast topology. a 16-bit backoffmask field is provided to allow the range of collision backoff values to be adjusted via management access. the backoffmask field contents are logically anded with the standard pseudorandom backoff value generated according to the ieee 802.3 backoff timer computation algorithm. the uppermost 6 bits of the backoffmask must be set to zero. the lower 10 bits should normally be set to all-ones, if the ieee 802.3 standard backoff algorithm (which specifies a range of 0 to 1023 slot times, inclusive) is to be adhered to; however, smaller ranges of backoff values may be generated by reducing the number of '1' bits set in this mask. the portflags field supplies several port-specific control bits that are used to determine the operating mode of the switching firmware when handling ethernet frames that are received from or transmitted to this port. this field is formatted as: 76 5 43210 backpen special type reserved txblkd rxblkd backprn backpen: if set, indicates that backpressure flow control is enabled for this port. this bit is normally set via a configuration parameter at system initialization time. special: if set, indicates that the data descriptors created for ethernet frames received on this mac channel should have the special flag bits set in their flags fields, causing them to be specially handled by the switching firmware. normally set to zero. type: this 2-bit field is used to initialize the 2-bit frame type subfield in the flags fields of data descriptors corresponding to ethernet frames received on this mac channel. normally set to 01 binary, corresponding to unicast frames received on a local mac channel. txblkd: if set, indicates that the mac channel is blocked to transmit; i.e., no frames pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 87 can be transmitted out this mac channel. normally used by the spanning tree algorithm. rxblkd: if set, indicates that the mac channel is blocked to received; i.e., frames received on this mac channel must be discarded. normally used by the spanning tree algorithm. backprn: if set, indicates that backpressure flow control is running for this port. the remainder of the local port descriptor holds per-port counters that are maintained and updated by the switching firmware in order to support the snmp and rmon mib statistics. a total of 11 32-bit counters are implemented. the switch processor caches the local port descriptor during normal operation. the in- memory copy of the local port descriptor, therefore, is likely to be 'stale' (i.e., outdated by information in the switch processor's data cache). the local port descriptor should preferably be read, if desired, by using the message interface maintained by the switch processor. if the contents of the local port descriptor must be directly read over the pci bus, the switch processor data cache must be flushed prior to the read, again via the message interface, which is described later. port descriptor counter structure the 96-byte port descriptor counter structure is considered to be an auxiliary data structure to the local port descriptor. this structure contains various error and collision counters that are infrequently updated during normal operation. the purpose of separating these counters from the local port descriptor structures is to reduce the amount of data that must be cached in the switch processor data cache: the port descriptor counter structures are not cached by the switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 88 each port descriptor counter structure is formatted as follows: 31 24 23 16 15 8 7 0 byte offset singlecollide 0 multcollide 4 latecollide 8 collideabort 12 rxerroroctets 16 alignerrors 20 crcerrors 24 dribbleframes 28 ovferrors 32 oversizeerrors 36 jabbererrors 40 shorterrors 44 fragerrors 48 limiterrors 52 txerrors 56 reserved 60 rxbcstframes 64 rxbcstoctets 68 rxfloodframes 72 rxfloodoctets 76 rxmcastframes 80 rxmcastoctets 84 reserved 88 reserved 92 singlecollide: 32-bit count of single collisions encountered when attempting to transmit frames out this mac port. only valid in half-duplex mode. multcollide: 32-bit count of multiple collisions encountered when attempting to transmit frames out this mac port. only valid in half-duplex mode. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 89 latecollide: 32-bit count of late collisions encountered when attempting to transmit frames out this mac port. only valid in half-duplex mode. collideabort: 32-bit count of transmit frames that were discarded due to excessive collisions for this mac port. only valid in half-duplex mode. rxerroroctets: 32-bit count of total number of octets for received frames that exhibited an error: this includes frames having alignment, crc, fifo overflow, oversize, jabber, short, collision fragment or buffer limit errors. alignerrors: 32-bit count of frames received on this mac port with alignment errors. a frame is deemed to have an alignment error if it is of valid length, and had an incorrect crc together with an odd number of framed data nibbles received on the mii interface. in this context, "valid length" means an actual frame length, excluding the preamble and sfd, between 64 and 1518 octets, inclusive. crcerrors: 32-bit count of frames received on this mac port with crc errors. a crc error is declared if a received frame is of valid length, had an even number of framed data nibbles as received on the mii interface, and failed the fcs check. dribbleframes: 32-bit count of the number of frames that were received with dribble errors. a frame is considered to have a dribble error if it has an odd number of framed data nibbles as received on the mii interface, but was otherwise non-errored (including the fcs check). note that frames with dribble errors will still be accepted and forwarded by the switching firmware, and will hence cause the rxvalidoctets counter to be incremented. ovferrors: 32-bit count of frames received on this mac port that were otherwise valid, but dropped due to receive fifo overflow. oversizeerrors: 32-bit count of frames received on this mac port that passed the fcs check but exceeded the preset maximum frame length limit (nominally1518 octets). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 90 jabbererrors: 32-bit count of frames received on this mac port that failed the fcs check and was longer than the preset maximum frame length. shorterrors: 32-bit count of frames received on this mac port that passed the fcs check but were below the preset minimum frame length (nominally 64 octets). fragerrors: 32-bit count of frames received on this mac port that failed the fcs check and were below the preset minimum frame length. these frames are typically collision fragments. limiterrors: 32-bit count of frames received on this mac port that were dropped due to lack of buffer space to hold them (i.e., as a result of congestion). lengtherrors: 32-bit count of frames received on this mac port that failed the ieee 802.3 length check (i.e., the length field within the frame was between 45 and 1499 inclusive, but did not match the actual frame length). txerrors: 32-bit count of frames that were dropped while being transmitted out this mac port. this counter is always zero during full-duplex operation; in half- duplex mode, it is incremented whenever a valid frame is dropped from the transmit fifo due to late collision, excessive collisions, or excessive carrier deference. rxbcstframes: 32-bit count of valid broadcast frames received on this port (that is, the destination address of the received frame is all-ones, corresponding to the ieee 802.3 broadcast address). rxbcastoctets: 32-bit count of octets in valid broadcast frames received on this port. rxfloodframes: 32-bit count of valid frames received on this port that were flooded to all ports on the spanning tree. a frame is flooded if the 48-bit destination address is not an ieee 802.3 group/functional address (i.e., the lsb of the address is zero, indicating a unicast destination) and an entry for the destination address is not present in the address table. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 91 rxfloodoctets: 32-bit count of octets in valid flood frames received on this port. rxmcstframes: 32-bit count of valid multicast frames received on this port (i.e., the 48-bit destination addresses of the counted frames are ieee 802.3 group/functional addresses, but not the broadcast address of all-ones). rxmcastoctets: 32-bit count of octets in valid multicast frames received on this port. the counters maintained within the port descriptor counter structure correspond to those required by the rmon and snmp mibs. the port descriptor counter structure occupies the memory locations described in the address map previously given. as the port descriptor counter structure is not cached, it may be read at any time via pci bus accesses. expansion port descriptor table a set of data structures, collectively referred to as the expansion port descriptor table , is associated with the pci expansion port. the expansion port descriptor table consists of eight 16-byte expansion port descriptors , each representing one of the (at most) eight elan 1x100 devices (or compatible devices, such as the elan 8x10) in the system. the expansion port descriptor table is used in conjunction with the transfer rings by the switching firmware to transfer frames and messages to other devices within the system. a single expansion port descriptor and the corresponding frame transfer queue is assigned to each device present on the pci bus; as there can be at most seven external devices (i.e., excluding the elan 1x100 itself), only seven of the eight expansion port descriptors are used, and the eighth descriptor is left untouched. each expansion port descriptor is hence effectively assigned to a logical device, with indices ranging from 0 through 7. the expansion port descriptor structures are mapped into the memory locations as given in the foregoing address map, with the structure corresponding to logical device index zero being mapped into the lowest memory address, and so on. note that the use of the expansion port descriptors is not limited to communicating with elan 1x100 devices. any device that implements the same transfer protocol can be interfaced to the elan 1x100 pci bus interface and assigned an expansion port descriptor (with the associated frame transfer queue), and the elan 1x100 device will transfer frames to this device without any special considerations. a detailed description of the frame transfer protocol, and the use of the expansion port descriptor and transfer pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 92 ring structures to sequence the transfer of data across the pci bus, is given in a subsequent section. an expansion port descriptor occupies 16 bytes, and is formatted as follows: 31 24 23 16 15 8 7 0 byte offset chipnum ringbase 0 ctrmask reserved 4 reserved reserved 8 remdd 12 ringbase: 24-bit pointer to first data descriptor in the transfer ring corresponding to this expansion port descriptor. this field is initialized with the base address fo the appropriate transfer ring during system boot, and remains unchanged thereafter. chipnum: 8-bit index assigned to remote chip corresponding to this expansion port descriptor. this field is set up at initialization time to contain a '0' for the first expansion port descriptor (i.e., with index 0), a '1' for the second expansion port descriptor, and so on. ctrmask: 8-bit mask that must be passed to the dma controller increment channel hardware when attempting to increment a request or acknowledge counter in the remote device. remdd: 32-bit pci address of next data descriptor pointing to frame to be transferred from remote device. generally, the uppermost 8 bits of this field remain constant, and give the upper 8 bits of the pci base address set for the remote device; the lower 24 bits vary, and give the offset of the data descriptor with reference to the pci base address. the chipnum and ctrmask fields are statically configured during initialization time. chipnum should be loaded with the index of the remote device, and is used by the firmware during consistency checks. the ctrmask field contains an 8-bit mask with the bit corresponding to the numeric index of the remote device set, and all of the other bits cleared. for example, ctrmask in expansion port descriptor zero (the first descriptor) will be set to 00000001 binary; that in the second expansion port descriptor will be set to 00000010 binary; and so on. the contents of ctrmask are loaded into the dma controller increment channel parameter registers when the switching firmware desires pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 93 to increment either the request or acknowledge counter in the remote device during expansion port frame transfers. the remdd field holds the 32-bit pci address of the data descriptor at the head of the transfer queue or ring assigned to this elan 1x100 in the remote device. this field is set up at system initialization time: the uppermost 8 bits are set to the 8 msbs of the pci base address of the remote device, while the lower 24 bits are set up to be equal to the value loaded into the ringbase field of the expansion port descriptor in the remote device (i.e., the address of the first data descriptor in the remote device's transfer queue or ring). after frame transfer from the remote device begins, the uppermost 8 bits of the remdd field remain the same, but the lower 24 bits are progressively updated by the firmware as frames are copied from the remote device. the frame transfer queue discipline described above makes the updating of this field simple: the nextdd field of the last data descriptor to be copied from the remote device is simply loaded into the lower 24 bits of the remdd field. as already noted, the expansion port descriptor corresponding to the index assigned to the elan 1x100 device itself (i.e., the device implementing the expansion port descriptor) is not used. thus expansion port descriptor 0 in device 0 is not used, expansion port descriptor 1 in device 1 is not used, and so on. (obviously, it is meaningless for a device to transfer frames to itself across the pci bus.) unlike local port descriptors, the data queued on an expansion port descriptor need not be restricted to ethernet frames. inter-device messages are exchanged by formatting them into packet buffers and then placing them on the expansion port descriptor transfer queues corresponding to the target devices. the data descriptor flags should be set up properly to ensure that the messages are handled specially by the remote devices, and not treated as normal ethernet frames. if the message is sufficiently compact, the packet buffers may be dispensed with and the entire message can be packed into the data descriptor; in this case, the firstpb field of the data descriptor should be set to a null. the expansion port descriptor structures are all cached by the switch processor in its data cache during normal operation; hence the in-memory copies of the expansion port descriptors may be out-of-date, and cannot be read directly from the pci bus interface in a reliable manner unless a data cache flush is performed first via the message interface. address hash table the elan 1x100 stores all learned or pre-configured ethernet addresses using a hash table approach. each entry in the address hash table is associated with a particular 48- bit ieee mac address. the table contains all of the information required to accept, process and switch packets to known (i.e., previously learned or set up) addresses. (in consonance with standard bridging practice, packets destined for unknown, i.e., not pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 94 previously seen or set up destinations must be flooded to all ports, or those determined using the standard ieee 802.1d spanning tree.) the hash table also serves to hold per- host statistics information. note that when multiple elan 1x100 devices are present in a system the hash table becomes a distributed data structure, with a separate table being maintained by each device and kept consistent by exchanging information among the different elan 1x100 devices according to a predefined protocol. the hash table consists of three types of data structures: an array, referred to as the hash pointer array , of between 256 and 8192 pointers; a set of 64-byte data structures called hash buckets , that hold the actual per-mac information for locally reachable hosts; and a set of 16-byte forwarding tags that hold abbreviated per-mac information for hosts reachable via external devices. each pointer in the hash array points to a linked-list of zero or more hash buckets and/or forwarding tags. each hash bucket or forwarding tag corresponds to a particular mac address; only one hash bucket or forwarding tag may be present for a given mac address in any device. in addition, only one hash bucket may be present for a given mac address in a complete system; however, multiple forwarding tags may be present in the various devices that point to this hash bucket. to access the hash bucket for a specific mac address, the hash lookup engine in the dma controller first creates a hash key and uses it to generate an index into the hash pointer array. the hash key is obtained by dividing the 48-bit mac address into three 16-bit blocks: 47 32 31 16 15 0 block 2 block 1 block 0 the three blocks are logically xored together to create a single 16-bit value, which is then logically anded with a configurable 16-bit bitmask to obtain the index into the hash pointer array. the purpose of the bitmask is to limit the range of the indices to the actual size of the hash pointer array: if there are 8,192 entries in the array, the bitmask should be defined such that the 13 lsbs are set to '1', and the 3 msbs are set to '0'. the hash lookup engine uses the computed index to locate the corresponding pointer within the hash pointer array, and reads the pointer to obtain the first element of the linked-list of hash buckets and/or forwarding tags that must be searched. it then scans the linked-list, comparing the complete 48-bit mac address to be resolved with the mac address fields within the hash buckets or forwarding tags, until the required hash bucket or forwarding tag is found (or no more entries are present in the linked-list). if a match is found, then the search is declared successful, and the memory address of the hash bucket or forwarding tag is passed to the switch processor; if the complete linked- pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 95 list is traversed without finding a match, then the search is considered to have failed (i.e., the specified source or destination mac address is not present in the address table), and an indication is accordingly passed to the switch processor by the hardware. on the elan 1x100, hash lookups are initiated at two different points in the frame switching process. firstly, the source and destination mac addresses of all frames received on the mac port are looked up in the address table automatically by the dma controller; this results in two hash lookup operations being performed for each incoming frame. secondly, another address table search is done if a frame was copied over the pci expansion bus and the learn flag bit is set in the flags field of the data descriptor associated with the frame. this hash lookup is done on the source mac address within the frame. 1 hash pointer array the hash pointer array is simply a linear array of 4-byte elements; each element contains a pointer to a linked list of hash buckets and/or forwarding tags. 31 24 23 0 unused pointer to bucket/tag (null if none) ... unused pointer to bucket/tag (null if none) 4n unused pointer to bucket/tag (null if none) 4n+4 unused pointer to bucket/tag (null if none) 4n+8 unused pointer to bucket/tag (null if none) 4n+12 unused pointer to bucket/tag (null if none) ... the hash pointer array occupies the locations in memory described by the address map given previously. initially, all the pointers in the array are set to zero (null), indicating that no mac addresses are present in the address table. as mac addresses are learned (or statically created), the hash buckets or forwarding tags corresponding to these addresses are inserted into the address table, and the relevant pointers in the array are updated to point to the linked-lists of hash buckets and/or forwarding tags. note that newly learned addresses are always placed at the head of any linked-list thus created. the size of the hash array, which determines the probability of collisions (i.e., the probability that multiple mac addresses will be associated with a single hash pointer 1 the setting of the learn bit is an indication by the remote device that it has determined that the source mac address of the frame under question was not seen before by the system, and needs to be entered into the address table; a hash lookup on the source mac address is done first as a precaution, to ensure that the mac address does not already exist in the table. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 96 array index, leading to the need for traversing a linked-list), is a configurable parameter that may be set at initialization. the contents of the hash array are never cached by the switch processor in its data cache; thus the hash array may be read via the pci bus interface without data consistency issues. hash buckets hash buckets are created to store frame handling and statistics information for all mac addresses that are discovered to be directly reachable via a local mac channel on the elan 1x100 device. each hash bucket contains, in addition to the ieee 802.3 mac address with which it is associated, various fields used in forwarding the incoming frame, controlling the aging process, and maintaining per-host statistics. the format of a 64-byte hash bucket is given below: error! no index entries found. 24 23 16 15 8 7 0 byte offset reserved nexthb 0 macaddr[31:16] macaddr[47:32] 4 multicastmask macaddr[15:0] 8 hbflags lpdptr 12 txframes 16 txoctets 20 rxerrorframes 24 rxmcstframes 28 rxfloodframes 32 rxbcstframes 36 rxucstframes 40 rxoctets 44 receivetimestamp[31:0] 48 createtimestamp[31:0] 52 receivetimestamp[47:32] createtimestamp[47:32] 56 reserved 60 nexthb: 24-bit pointer to next hash bucket or forwarding tag in linked-list; null if none. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 97 macaddr: 48-bit ieee 802.3 mac address associated with this hash bucket. multicastmask: 16-bit mask used to restrict multicasts directed to this mac address to a subset of the devices in the system. only valid for multicast mac addresses, as indicated by the proper setting of the hbflags field. lpdptr: 24-bit address of the local port descriptor assigned to the physical elan 1x100 port associated with this mac address (always the same for all hash buckets). hbflags: 8-bit per-mac control flags, formatted as described below. txframes: 32-bit count of unicast frames transmitted to this mac address. txoctets: 32-bit count of total number of bytes transmitted to this mac address. rxerrorframes: 32-bit count of frames received from this mac address with errors. rxmcstframes: 32-bit count of valid multicast frames (i.e., frames directed to ieee 802.3 group/functional addresses, excluding the broadcast address) received on this port. rxfloodframes: 32-bit count of valid flood frames received on this port. a frame is considered to be flooded if it is a unicast, but is directed to all ports in the system because the elan 1x100 does not have an entry for the destination mac address in its address table. rxbcstframes: 32-bit count of valid broadcast frames received on this port. broadcast frames are classified as frames with a destination mac address of all-ones. rxucstframes: 32-bit count of valid unicast frames received on this port. rxoctets: 32-bit count of total bytes (errored or otherwise) received on this port. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 98 receivetimestamp[31:0]: lower 32 bits of timestamp indicating when a frame was last received from this mac address. these bits are obtained directly from the clock register pair within the switch processor. receivetimestamp[47:32]: upper 16 bits of timestamp indicating when a frame was last received from this mac address. these bits are incremented under switch processor firmware control whenever a carry out of receivetimestamp[31:0] is detected. createtimestamp[31:0]: lower 32 bits of timestamp indicating when this hash bucket was originally created. these bits are obtained directly from the clock register pair within the switch processor. createtimestamp[47:32]: upper 16 bits of timestamp indicating when this hash bucket was originally created. these bits are set by the switch processor firmware using an internally extended version of the clock register pair. the nexthb field contains a 24-bit pointer to the next hash bucket (or forwarding tag) in the linked-list of hash buckets. it is null (all-zeros) if this hash bucket forms the end of the chain. the macaddr field spans two consecutive words, and contains the complete 48-bit mac address associated with this hash bucket; it is compared to the address extracted from the ethernet frame during the address table lookup process to ensure that the proper hash bucket has been found. the 16-bit multicastmask field is used to restrict broadcasts, multicasts and floods of packets directed to a given multicast mac address (i.e., when the macaddr field is set to an ieee group/functional address). the lower 8 bits of this field are always zero, and the upper 8 bits of the mask correspond to the eight possible devices in the system. a device is permitted to be part of a multicast if its corresponding bit in the multicastmask field is set to a '1'. (note that the bit in the multicastmask corresponding to the elan 1x100 device itself is always set to zero at initialization time.) the multicastmask field is logically anded with the global restriction mask managed by the spanning tree protocol entity, as well as the multicastmask field in the local port descriptor structure, to implement multicasts on a per-mac-address as well as per-port basis. it is ignored for unicast frames, or for hash buckets corresponding to source mac addresses in received ethernet frames. the lpdptr field contains a 24-bit pointer to the local port descriptor structure. it is provided for cross-compatibility purposes with the elan 8x10 device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 99 the hbflags field supplies several mac-address-specific control bits that are used to determine the operating mode of the switching firmware when handling ethernet frames that are received from or transmitted to this mac address. this field is formatted as: 7 654321 0 reserved special type reserved noage special: if set, indicates that the frame data must not be processed by the normal switching firmware, but must be handled specially by external code. normally zero. type: this 2-bit field denotes the type of mac address (and hence the disposition of the ethernet frame directed towards the mac address). it is interpreted as follows: type interpretation 00 invalid for hash buckets, reserved for forwarding tags 01 unicast mac address reachable via local mac channel 10 invalid for hash buckets, reserved for forwarding tags 11 broadcast mac address reachable via local mac channel the type field is only valid if the special bit is clear, indicating that the frame can be treated as a normal ethernet frame. noage: if set, denotes a permanent hash bucket (i.e., one that the aging process is not permitted to remove). normally cleared for addresses learned by the elan 1x100. the receivetimestamp field holds a 48-bit timestamp that records the absolute time at which a frame was last received from the source host with a mac address corresponding to this hash bucket. the timestamp has a resolution of 1 microsecond and a range of approximately 3258 days. it is used during the aging process to locate hash buckets that have not been refreshed for some time, and are thus candidates for removal. the switch processor updates the receivetimestamp field whenever a valid ethernet frame is received and the hash lookup engine resolves the source mac address in the frame to the given hash bucket. the upper 16 bits of the timestamp (bits 47:32) are written with the software maintained real time clock. the 48-bit timestamp value is generated by concatenating the 32-bit clock real-time clock register in the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 100 switch processor with a firmware-maintained 16-bit variable that holds the carries out of the clock register. the createtimestamp field holds a 48-bit timestamp indicating when the hash bucket was created and inserted into the address table. this value is generated in a similar manner to the receivetimestamp field, using the 32-bit hardware clock register coupled with a firmware count of carries to extend the clock register value to 48 bits. it is principally used as part of the rmon mib. the remainder of the local port descriptor holds per-mac counters that are maintained and updated by the switching firmware in order to support the rmon mib statistics. a total of seven 32-bit counters are implemented. note that the rxerrorframes counter is only updated if sufficient bytes of the frame are received to permit the hash lookup engine to successfully resolve the source hash bucket. the switch processor does not cache any hash bucket at any time in its internal data cache. it is therefore possible to read the contents of any hash bucket via the pci bus interface without data consistency issues. forwarding tags a 16-byte forwarding tag is created whenever it is necessary to record that a particular mac address is reachable by an external device (such as another elan 1x100), and frames directed to this mac address should be directed to that device via the pci expansion port. forwarding tags have the following format: error! no index entries found. 24 23 16 15 8 7 0 byte offset chipnum nextft 0 macaddr[31:16] macaddr[47:32] 4 reserved macaddr[15:0] 8 ftflags srchashbkt 12 nextft: 24-bit pointer to next forwarding tag (or hash bucket) in linked-list; null if none. chipnum: 8-bit index assigned to remote device corresponding to this forwarding tag. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 101 macaddr: 48-bit ieee 802.3 mac address associated with this forwarding tag. srchashbkt: 24-bit address of the target hash bucket within the remote device that contains the primary frame handling and statistics information for this mac address. ftflags: 8-bit per-mac forwarding control flags, formatted as described below. the nextft field contains a pointer to the next forwarding tag (or hash bucket) in the linked-list of forwarding tags. it is null (all-zeros) if this forwarding tag forms the end of the chain. the macaddr field spans two consecutive words, and contains the complete 48-bit mac address associated with this forwarding tag; as in the case of the hash bucket, the macaddr field is compared to the address extracted from the ethernet frame during the address table lookup process to ensure that the proper forwarding tag has been found. the chipnum field holds the index of the external device corresponding to this forwarding tag, i.e., the device to which frames directed to this mac address should be sent. the chipnum field is set up when the forwarding tag is inserted into the address table with the id of the device requesting that the tag be created. the srchashbkt field contains the 24-bit memory address of the actual hash bucket that holds the necessary physical port routing information and the per-mac statistics associated with this mac address. this address is valid only in the memory address space of the remote device , and has no significance to the elan 1x100 containing the forwarding tag. the remote device supplies the information placed in the srchashbkt field when it requests that a forwarding tag be created during the learning process. if the destination mac address of a received ethernet frame resolves to a forwarding tag, then the elan 1x100 device will transfer the frame to the remote device indicated by the chipnum field in the forwarding tag, and will also place the srchashbkt value in the hashbkt field of the data descriptor associated with the frame. the remote device is expected to use the hash bucket address passed by this elan 1x100 to avoid having to perform yet another hash lookup in its own version of the address table; instead, it will locate the hash bucket indicated by the hashbkt field of the data descriptor, verify that it is indeed valid, and use the information within the hash bucket to switch the frame. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 102 ftflags supplies control bits that are used to determine the operation of the switching firmware when handling ethernet frames that are directed to this mac address. this field is formatted as: 7 6543210 reserved special type reserved special: if set, indicates that the frame data must not be processed by the normal switching firmware, but must be handled specially by external code. normally zero. type: this 2-bit field denotes the type of mac address (and hence the disposition of the ethernet frame directed towards the mac address). it is interpreted as follows: type interpretation 00 unicast mac address reachable via a remote device 01 invalid for forwarding tags, reserved for hash buckets 10 broadcast mac address reachable via a remote device 11 invalid for forwarding tags, reserved for hash buckets the type field is only valid if the special bit is clear, indicating that no special processing is required for frames directed to this forwarding tag. the type field of the forwarding tag corresponding to the destination mac address is generally used to set up the type subfield of the flags field of the data descriptor (and thus to switch the frame). note that it is an error for a source mac address to resolve to a forwarding tag during the address lookup process. this indicates that the owner of the mac address has apparently moved from a port on a remote device to a port on this elan 1x100. the switch processor will, in this case, announce a topology change situation, and go through the topology change update process required. the switch processor does not cache any forwarding tag at any time in its internal data cache. it is therefore possible to read the contents of a forwarding tag via the pci bus interface without data consistency issues. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 103 free pools during normal frame switching operations, the elan 1x100 must dynamically allocate blocks of memory to hold packet buffers, data descriptors, hash buckets, and forwarding tags. (the memory allocation required to support the rtos, and snmp and rmon agents is not considered here; this type of memory allocation is expected to be handled as part of the rtos.) these memory blocks are drawn from four free memory pools: a packet buffer pool , a message descriptor pool , a hash bucket pool and a forwarding tag pool . all the pools consist of constant-sized blocks of memory linked together by means of pointers in the normal fashion. the packet buffer pool consists of a linked-list of (nominally) 80-byte memory blocks on 16-byte boundaries, and is used to supply packet buffers for holding received ethernet frames. note that the block size may be changed between 64 and 240 bytes, in increments of 16 bytes, via a configurable parameter at initialization time. the head of the packet buffer pool is actually maintained by the dma controller; an internal hardware register in the dma controller is set up at initialization time to point to the first free buffer in the linked-list, and the dma controller allocates blocks from the list as required to hold frames received on the mac port. deallocation of the packet buffers to the free pool is performed by the switch processor firmware after frames have been completely transferred across the pci bus (that is, the frame has been acknowledged to be read by all remote devices to which the frame was to be forwarded), or been dropped for assorted reasons. the free message descriptor pool is used for supplying message descriptors, used for tracking management frames or control/status messages. it is created from a linked- list of 16-byte fixed-size memory blocks, and is maintained entirely by the switch processor firmware. blocks are allocated from this pool as required when a message descriptor must be created to hold information for messages received from external devices over the pci expansion bus, or for management frames that have been received either on the mac port or from a device on the pci bus. the hash bucket pool is composed of a linked-list of 64-byte blocks that are intended to be used to create hash buckets when mac addresses are learned. one minor difference between this pool and the others is that the blocks in this pool are pre- formatted for rapid learning; all of the fields of the hash buckets in this pool, with the exception of the mac address and the local port descriptor address, are initialized to their default values. this allows the learning process to simply allocate a free hash bucket, fill in the mac address and local port descriptor pointer, and place the hash bucket into the address table, thereby minimizing the time spent formatting the hash bucket. when hash buckets are deallocated to the free hash bucket pool (during aging, or topology changes), they are again re-formatted before being placed on the free pool. as the aging and topology change handling are principally non-time-critical background tasks, the additional time required to pre-format the hash buckets is not a significant issue. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 104 the forwarding tag pool is constructed from a linked-list of 16-byte blocks, and supplies forwarding tags that are required during the learning of mac addresses reachable by remote devices. forwarding tags are allocated by the switch processor firmware during the learning process, and deallocated (again by the switch processor firmware) when they are removed from the address table. removal of forwarding tags takes place only after their parent source hash buckets (on the remote devices) are removed. the sizes and locations of the various free pools are completely configurable via parameters in the boot image, and can be adjusted by the system implementer as desired. these parameters implicitly determine the total amount of buffering in the system, the broadcast frame reception rate, the number of mac addresses supported, and so on. pool-empty handling the parameters supplied during the initialization process (such as the number of addresses to be learned, the packet buffers that can be consumed, etc.) should be selected for the system such that none of the four free pools will be permitted to become empty during normal operation. this is not, however, always guaranteed. the elan 1x100 switching firmware thus checks for pool-empty conditions and performs recovery processing as required to deal with the situation. it is illegal for the free packet buffer pool to become empty at any point, as the dma controller hardware always requires that at least one free packet buffer be present in this linked-list. 1 the dma controller hardware itself will not violate this rule; if at any time, the dma controller determines that there is only one packet buffer left in the free packet buffer pool, then that packet buffer will not be allocated. (if a frame is being received, or is subsequently received, then a receive overflow error will be declared.) if, however, the free packet buffer pool becomes completely empty (e.g., due to some system failure), then the dma controller will notify the switch processor, which will in turn declare a fatal system error and attempt to initiate a hardware reset to recover from this condition. the free message descriptor pool, hash bucket pool, and forwarding tag pool are all controlled entirely by the switch processor firmware. the recovery process for one or more of these pools becoming empty during operation is less drastic than a hardware reset; in most cases, normal system operation can continue, with some degradation in system response. if the firmware detects that the free message descriptor pool is empty, then it will not accept any more messages or management frames from other devices, and will discard 1 this is due to the mechanism used by the dma controller to allocate and deallocate packet buffers from the free pool. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 105 any frames that are received but need to be handled specially. it will not, however, cause the remote devices on the pci bus to discard messages that have been queued for this elan 1x100; instead, it will refuse to read any more data from the devices in question. if the free hash bucket pool is emptied (i.e., the maximum number of mac addresses have been learned from frames arriving over the local mac port), then the switching firmware will simply cease to learn any more mac addresses from the local port. frames arriving with new source mac addresses will be forwarded as usual; however, frames that are subsequently directed towards these new (and unlearned) mac addresses will be flooded, as no entries will exist for them in the address table. this effect is comparatively benign, as no frames are lost, and only a small performance degradation is encountered. if the free forwarding tag pool is exhausted, then a similar process is used to handle this condition. in this case, however, the elan 1x100 will refuse to learn mac addresses contained within frames arriving over the pci expansion port (i.e., with the learn bit in the data descriptor flags field set). again, frames that are subsequently directed to these unlearned addresses will simply be converted into floods. spanning tree support data structures upon start-up, if spanning tree is enabled, the elan 1x100 creates a set of data structures required for implementing the ieee 802.1d spanning tree algorithm. (in a system comprised of multiple elan 1x100 and elan 8x10 devices, only the master device constructs the spanning tree data structures and implements the spanning tree algorithm; the slave devices exchange data with the master device and transmit packets on its behalf, but do not maintain the spanning tree data structures.) two different data structures are used by the spanning tree algorithm: a per-bridge data structure, only one of which is present in a system, and a per-port data structure, which is replicated for each port in the system. further description of the spanning tree data structures is tbd. broadcast restriction mask a special data structure, referred to as the broadcast restriction mask , is used by the elan 1x100 to limit packet broadcasts in response to the results of the spanning tree algorithm. this mask consists of sixteen bits: eight bits correspond to a port mask and eight bits correspond to a device mask. the elan 1x100 has only one physical port, and hence the lower 8 bits of the broadcast restriction mask are set to zero. the remaining eight bits are assigned to the eight possible external devices connected to the pci expansion bus, as shown below: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 106 1514131211109876543210 d7d6d5d4d3d2d1d000000000 the eight device-related bits are denoted as d0 through d7. note that the device- related bit corresponding to the given elan 1x100 device itself must always be zero, as it is not permissible for an elan 1x100 device to send broadcasts to itself across the pci bus. in addition, bits corresponding to non-existent devices will be set to zero if there are less than eight devices in the system. when a broadcast or multicast frame, or one directed to an unknown mac address (which must be flooded) is received, the elan 1x100 inspects the broadcast restriction mask to determine the permissible destinations to which the frame may be sent. the mask is initialized as required upon power-on, and subsequently modified by the spanning tree algorithm or system manager to remove specific ports and devices from the broadcast topology. note that hash buckets for multicast mac addresses contain their own restriction masks, which are logically anded with the global broadcast restriction mask to further limit the broadcast topology; this feature may be used to implement multicast groups. in addition, broadcast restriction on a per-source-port basis is made possible by a similar multicast restriction mask in each of the local port descriptors, which is also anded into the global broadcast restriction mask. rtos requirements this section details the general requirements and specific data structures of interest that are implemented by the optional real-time operating system. this section is tbd. udp/ip protocol stack requirements this section describes the data structures created and maintained in order to support the udp/ip protocol stack that is required by the snmp agent to communicate with management platforms. it also describes the communication mechanisms used to exchange service data units (sdus) with the udp protocol layer. this section is tbd. snmp requirements this section gives a brief overview of the general requirements of the snmp agent with regard to data structures used to support the mib and the agent itself. this section is tbd. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 107 storage requirements the local ram storage requirements of the elan 1x100 are highly dependent on the system configuration (e.g., the amount of buffering required per port) as well as the various options selected, such as whether an snmp agent is implemented or not. some guidelines that may be used for estimating the amount of ram for various system configurations is presented here. the storage requirements may generally be divided into two categories: ram space required for basic ethernet frame switching operations, including operating data areas and memory pools; and the ram space required to support an snmp agent and the associated mib, rtos and udp/ip stack. general frame switching requirements for general frame switching operations, the storage requirements are limited to the switch processor operating environment, the transfer rings, and the free pools (i.e., the free packet buffer pool, the free data descriptor pool, the free hash bucket pool and the free forwarding tag pool). in addition, a small amount of memory is required in order to copy the system boot image from eprom or eeprom to working ram. the requirements for each type of structure are summarized in the following table: structure size, each quantity required suggested quantity operating environment 43 kb single block of memory starting at address 0x000000 1 packet buffers 80 bytes per-port buffer capacity (equals number of packet buffers multiplied by the size of the data payload within a packet buffer) about 50% of available memory transfer rings 16 bytes (per element) number of frames or messages that can be queued for device corresponding to each transfer ring, multiplied by number of devices one per packet buffer in system message descriptors 16 bytes number of control/status messages and messages that can be accepted at a time 512 hash buckets 64 bytes number of mac addresses that can be learned from frames received on the local mac port about 25% or avail. mem. forwarding tags 16 bytes number of mac addresses that can be learned from frames received over the pci bus equal to hash buckets boot image copy 32 kb temporary use; held reserved for simplicity 1 the computation of the number of elements (data descriptors) required for each of the transfer rings used to queue frames destined for external devices is somewhat difficult. the upper bound on this number, obviously, is the number of packet buffers that are present in the free pool; if it is assumed that the number of messages that do not pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 108 require any packet buffers is negligible compared with the number of frames and messages requiring packet buffers, then clearly the maximum number of entries that can be made on any one transfer ring is limited to the number of packet buffers that can be queued, which in turn cannot exceed the number of packet buffers in the local memory. this assumes the worst case of one packet buffer per frame; if larger frames are being queued, the number of elements used in the transfer rings drops proportionally. in order to guarantee that under no circumstances would the elan 1x100 have to drop a frame due to the lack of queueing resources, therefore, the number of elements in each of the transfer rings should be equal to the number of packet buffers. this is especially significant in systems where flow-control is enabled; if the local port buffer limit does not reach the flow-control threshold before the transfer rings run out of elements and frames begin to be dropped, it is likely that flow-control will never be initiated but continuous frame loss will take place. in addition, the number of elements in each transfer ring should be a power of 2. the total number of rings required is one less than the number of devices in the system; thus a system with 8 devices would require 7 rings to be set up. as an example, consider the memory requirements for an elan 1x100 in a typical system having the following parameters: at least 160 kb of frame buffer storage for the local mac port an address table capacity of up to 2048 mac addresses a total of four devices in the system (e.g., two elan 1x100 chips coupled with two elan 8x10 chips) assuming that the recommended values for the various types of memory regions are followed, the parameters for such a system would be: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 109 structure qty needed storage operating environment 1 43 kb packet buffers 2048 160 kb transfer rings (3) 2048/ring 96 kb message descriptors 512 8 kb hash buckets 2048 128 kb forwarding tags 2048 32 kb boot image copy area 1 32 kb total 499 kb this amount of memory fits well into a base configuration with 512 kb of sram. an example memory map is as follows (note that addresses increase downwards): pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 110 0x000000 switch processor operating environment 0x00a8ff 0x00a900 packet buffers 0x033fff 0x034000 data rings 0x04bfff 0x04c000 hash buckets 0x0636ff 0x04c000 hash buckets 0x0636ff 0x063700 forwarding tags 0x07503f 0x075040 unused space 0x077fff 0x078000 boot image copy area 0x07ffff the small amount of wasted space at the top of the address map is not significant. the various start addresses of the memory blocks (with the exception of the switch processor operating environment) are entirely arbitrary, and can be modified at will via the configuration header file supplied during the boot image creation process. managed system requirements this section discusses the memory requirements for supporting the rtos, the udp/ip stack, the snmp agent, and the mib implemented by the elan 1x100. this section is tbd. switching system initialization prior to beginning ethernet frame switching operations, it is necessary to initialize the various data structures (primarily the variables in the switch processor operating pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 111 environment) and internal device registers to the appropriate values, and also to set up the free pools required for dynamic memory allocation. this section describes the initialization process in detail. this section is tbd. frame switching process if a frame received on a physical port of a elan 1x100 device is addressed to a destination host connected to a mac port of remote device (such as an elan 8x10 or elan 1x100), then the frame will be passed to the external device via the pci expansion bus interface. the frame will also be passed to one or more external devices if it is a broadcast, multicast or flood (i.e., the destination mac address is unknown). otherwise, the frame will be filtered. frame switching on the elan 1x100 is carried out in two stages: the source elan 1x100 receiving the frame appends the frame to the transfer ring that it maintains for the destination device (and signals the destination device that another frame is available); the destination device is then expected to copy the data from the source elan 1x100 to its own memory space, and notify the source elan 1x100 when the transfer is complete (i.e., acknowledge the transfer). the destination device is thereafter completely responsible for subsequently transmitting the data on the correct ethernet link. note that broadcast or multicast transfer to multiple remote devices is done by having each destination device separately copy the same frame across the pci bus to their own memory spaces, and separately acknowledge the copy to the source of the frame. this will be followed by multiple transmissions of the frame over the local port or ports within the destination devices, without any further use of the pci bus. a bandwidth multiplication effect is thus obtained when the destination device has multiple physical mac ports (such as the elan 8x10 chip), as a single copy of the frame over the pci bus can result in multiple transmissions within the destination device. request and acknowledge counters and protocol the elan 1x100 (and other devices that expect to communicate with the elan 1x100) implements a set of hardware counters that assist in the signalling across the pci bus. a total of eight request counters and eight acknowledge counters are implemented, one corresponding to each device in the system. these counters are mapped into the upper 64 kb of the 16 mb address space assigned to each elan 1x100 device, and are incremented as required to notify target devices that frames are available to be transferred, or that frames have been transferred and the memory resources used by them may be freed. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 112 a relatively simple protocol is followed when transferring frames between elan 1x100 devices across the pci bus. the following figure shows a high-level view of the handshake employed: receive frame copy data from source transmit frame increment request counter across pci increment ack. counter across pci free packet buffers in frame source destination the frame transfer handshake is initiated when a source elan 1x100 device receives a valid frame from the mac channel and determines that it is destined for an external destination device. at this point, it performs a single-word write across the pci bus to increment a special counter in the destination device. this counter is referred to as the request counter , and serves to notify the destination device that a frame or message is ready to be transferred across the pci bus from the source device. when the destination device detects that the request counter has been incremented, it copies the frame data from the head of the transfer queue maintained for it by the source device across the pci bus (via a pci memory read command) to buffers in its local memory using a dma channel. the destination then performs another single-word write across the pci bus to another special counter in the source, referred to as the acknowledge counter . this write automatically increments the acknowledge counter. once this operation is done, the destination device is free to go ahead and transmit the newly copied frame from the buffers in its local memory space. when the source device detects that the acknowledge counter has been incremented, it knows that the destination device has successfully copied the frame data out of the source buffers, across the pci bus, and into local buffers at the destination. the source pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 113 buffers are no longer needed; the source device can then free the buffers to the free pool, to be used for the storage of some subsequent frame. note that the use of counters rather than flags or registers permits multiple requests or acknowledges to be outstanding at any device without problems. each destination device must thus maintain a request counter that the source device can increment, and each source device must maintain a counter that the destination can increment in acknowledgement. if the "destination" device wishes to send frames back to the "source" device, then a mirror set of request and acknowledge counters must be implemented in the devices, and the same protocol works but in mirrored fashion. to extend the protocol to support multiple devices in the system, a bank of request counters and a bank of acknowledge counters are built into each device: each device in the system contains eight request counters and eight acknowledge counters, thereby permitting systems to be built with up to eight inter-communicating devices. the counters are mapped into the pci memory address space starting at offset 0xffff00 hex from the base address assigned to the device, as follows: 0xzzffffff internal registers, etc. 0xzzffff40 0xzzffff3c acknowledge counter #7 0xzzffff38 acknowledge counter #6 0xzzffff34 acknowledge counter #5 0xzzffff30 acknowledge counter #4 0xzzffff2c acknowledge counter #3 0xzzffff28 acknowledge counter #2 0xzzffff24 acknowledge counter #1 0xzzffff20 acknowledge counter #0 0xzzffff1c request counter #7 0xzzffff18 request counter #6 0xzzffff14 request counter #5 0xzzffff10 request counter #4 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 114 0xzzffff0c request counter #3 0xzzffff08 request counter #2 0xzzffff04 request counter #1 0xzzffff00 request counter #0 0xzzfffeff external local memory and internal registers 0xzz000000 note that the component of the 32-bit pci address marked "zz" (as in 0 xzz000000, for example) represents the base address loaded into the uppermost 8 bits of the memory base address register. as shown, the eight request counters occupy consecutive 32-bit locations from an offset of 0xffff00 to 0xffff1c hex from the base address assigned to the device in pci address space; the eight acknowledge counters occupy locations from an offset of 0xffff20 to 0xffff3c hex. the address of acknowledge counter #0 may thus be obtained by adding 0x20 hex (i.e., 32 decimal) to the address of request counter #0, and so on. each pair of request and acknowledge counters marked with a given index is dedicated to a particular device in the system. if the devices are numbered from 0 through 7, and referred to as device #0, device #1, and so on, then request counter #0 and acknowledge counter #0 are dedicated to device #0 in every device; request counter #1 and acknowledge counter #1 are dedicated to device #1; and so on. the use of the counters is as follows. if, for example, chip #3 wishes to transfer a frame to chip #5, it will increment request counter #3 implemented by chip #5 (signalling to chip #5 that chip #3 has a frame pending for transfer). chip #5 determines by the index of the request counter the source of the data (i.e., that it comes from chip #3), performs the necessary transfer across the pci bus, and then acknowledges the transfer by incrementing acknowledge counter #5 implemented by chip #3. this signals to chip #3 that chip #5 has read a frame from the former's local memory, and the packet buffers may be freed. note that one of the eight pairs of request and acknowledge counters will always be unused in each device in the system. in chip #0, for instance, request and acknowledge counters #0 will never be incremented (incrementing request counter #0 in chip #0 would imply that chip #0 was attempting to send a frame to itself across the pci bus, which is clearly redundant). essentially, the pair of request and acknowledge counters with an index that equals that of the chip itself will never be incremented. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 115 if bilateral and uniform exchanges of frames are required in the system, then it is obvious that at most eight devices (one for each pair of request/acknowledge counters) can be supported. the following table shows, as an example, a three-device system with devices numbered from 0 through 2, and identifies the request and acknowledge counters that are incremented when a frame is transferred from any source device to any destination device: dest = chip #0 dest = chip #1 dest = chip #2 src=chip #0 n/a n/a req id = 0 ack id = 1 req id = 0 ack id = 2 src=chip #1 req id = 1 ack id = 0 n/a n/a req id = 1 ack id = 2 src=chip #2 req id = 2 ack id = 0 req id = 2 ack id = 1 n/a n/a in the table above, "req" refers to the index of the request counter, and "ack" refers to the index of the acknowledge counter. note that the request counter is always incremented in the destination device, and the acknowledge counter is always incremented in the source device. the index of the chip making the request or returning the acknowledge can be obtained by simply inspecting the index of the incremented counter. an inspection of the table above will reveal that the indices of the request and acknowledge counters that are incremented by any particular chip are always the same. thus, for example, chip #1 will always increment request counter #1 in any other device when acting as a source of data, and will always increment acknowledge counter #1 in another device when acting as a destination and acknowledging the receipt of data. the foregoing has dealt with the use and configuration of the hardware communication means, i.e., the request and acknowledge counter banks. the situation for the actual data transfer is substantially simpler, as the elan 1x100 hardware and firmware place no restrictions on the pci addresses from which data copies may be done. once a particular request has been mapped to a specific source chip via the request counter index by any external device, the 32-bit pci address from which the data transfer must be performed is defined by the 32-bit remdd field of the expansion port descriptor assigned to track transfers from that chip. thus the only hard limitation on the number of devices that may be supported by an elan system is set by the number of request and acknowledge counters that are implemented in the elan 1x100 and elan 8x10 chips. it should be noted that the assignments of counter indices to devices (as well as the association of devices with actual pci addresses) is performed statically at initialization time by the boot image executed by every elan device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 116 hardware support for transfer protocol in addition to the request and acknowledge counters used to set up the transfer handshake between two elan switch devices. the elan 1x100 also contains special hardware that increases the efficiency of the switching firmware when initiating and controlling this transfer. this hardware is built into the dma controller increment channel logic. when a frame is to be forwarded to a remote elan switch device, the switch processor in the elan 1x100 does not actually write information into the physical memory holding the transfer ring corresponding to the remote device. instead, it writes the information for the various fields of the data descriptor corresponding to the frame or message into a special set of registers in the dma controller, and notifies the dma controller of the target transfer queue to update by copying the chipmask field from the corresponding expansion port descriptor into another special register. once this is done, the involvement of the switching firmware in the transfer notification has ended. the dma controller will then determine the next free element in the specified transfer queue to use and write the information supplied by the switch processor into the element to create a data descriptor in the correct format. it will then perform a write operation across the pci bus to increment the proper request counter in the specified device. this will complete the request portion of the handshake; the remainder of the handshake proceeds as previously described. to facilitate the updating of the transfer rings in the proper sequence, the dma controller maintains hardware pointers to the first and last element in each transfer ring. when an element is allocated and formatted into a data descriptor, the write pointer associated with that transfer ring is incremented by 16 to point to the next element; when an acknowledge has been received from the remote device after successfully completing the data transfer, the dma controller will increment the read pointer for that transfer ring, again by 16. the hardware read and write pointers are used by the dma controller to ensure that unread elements in the transfer rings are never overwritten. multicast and broadcast frame queueing is supported by an additional feature. when a multicast or broadcast frame is to be queued on the transfer rings, the switch processor firmware writes the required contents of the data descriptors to be created on the transfer rings to dma controller registers (as before). it then writes a bitmask to a special register; the bitmask contains a '1' bit for each of the devices to which the multicast or broadcast is directed. (the bitmask is taken directly from the upper 8 bits of the multicastmask fields.) the dma controller will then update all of the transfer rings as indicated by the bitmask with the proper information, and will increment the request counters in all of the target devices. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 117 general frame transfer sequence the following diagram details the sequence of events when switching a unicast frame from a mac port on the source elan 1x100 to a mac port on a remote elan switch device via the expansion bus. (the same general sequence holds even if the destination device is not an elan 1x100 or elan 8x10 chip, as all devices that expect to communicate with the elan 1x100 must follow the same protocol.) note that if a broadcast frame is sent to two or external devices, then the frame reception and processing steps remain the same within the source device, but the frame transfer steps are repeated for each additional remote elan switch device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 118 frame receive begins dma fills pbs & looks up mac addrs frame receive done classify frame and update src statistics set up dma increment channel attach frame to pci transfer ring(s) check frame, decrement buffer count increment request counter dma transmits frame frame transmit done, interrupt read distrib. fifo and update dst stats increment src port buffer count read frame data from dma source receive process destination transmit process 1 2 3 4 5 6 7 8 9 process req. ctr. interrupt dma reads dd, issues tx hdr intr. set up pci dma transfer dma starts copy of dd + pbs to tx fifo read dd, classify frame, write code to disp. fifo incr. ack. counter destination transfer process 13 14 15 18 19 free src pbs source acknowledge handler 17 frame reaches head of tx fifo dma firmware firmware dma firmware firmware dma firmware 16 10 11 12 receive interrupt dma request counter interrupt transmit header interrupt save hb ptr in distrib. fifo dma done with frame transfer ack. counter interrupt transmit done interrupt dma pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 119 1. the source elan 1x100 device in the system begins receiving an ethernet frame on its mac channel; the frame is intended for a destination entity connected to a port on another elan 1x100 device (the destination device). the elan 1x100 mac channel converts and places the incoming data into the mac interface receive fifo until the end of the frame has been reached. 2. the dma controller allocates one or more packet buffers from the free packet buffer pool to hold the frame and fills them with data words copied from the mac channel fifo, computing the required 32-bit crc over the frame at the same time. when the 14-byte frame header has been received, the dma controller uses the hash table lookup mechanism to scan the address table and obtain the pointers to the source and destination address table entries for the mac addresses in the frame. note that the destination address table entry in this case must be a forwarding tag, as the frame is destined to be transferred across the pci bus to another device. the source address table entry (if one exists) must be a hash bucket. 3. the frame reception process continues until the frame has been completely received and transferred to packet buffers. when reception terminates on the mii bus, the dma controller flushes all frame data from the mac receive fifo to the packet buffers and notifies the switch processor of the received frame via an interrupt, referred to as the receive frame interrupt .. the dma receive channel will not start reading frame data for another ethernet frame until the switch processor re-enables it; this is to prevent the next receive frame from overwriting any registers associated with the prior frame. 4. the switch processor executes the receive frame interrupt service routine in the switching firmware in response to this interrupt. the first action of the service routine is to read out the contents of the appropriate dma controller receive channel registers, and then re-enable the dma channel to allow it to receive more frames. the receive interrupt service firmware then checks the status code returned by the dma to determine whether the frame is errored, and performs the necessary processing as indicated. note that the mac channel hardware can begin receiving the next frame into its 64-byte fifo buffer even if the switching firmware has not yet re-enabled the dma controller after the reception of a previous frame; a receive error will only occur if the mac channel fifo overflows before the dma controller has been re-enabled. 5. if a valid frame has been received, the firmware verifies that the port buffer allocation limit in the maxbuffers field of the local port descriptor has not been exceeded. if the allocation limit has been exceeded, and flow control has been enabled, the appropriate flow control procedure will be performed, depending on whether the channel is operating in full-duplex or half-duplex mode. if flow control has not been enabled, then the frame will simply be dropped (and statistics updated) when the allocation limit is exceeded. if the frame is invalid, then the appropriate statistics are updated and the frame is simply dropped. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 120 6. the firmware then proceeds to check the source hash bucket pointer returned by the dma controller for consistency, and will announce a topology change or learn a new address based on the results. it will also update the aging timestamp in the source hash bucket (if a valid one exists). the standard filter check is performed to insure that the source and destination ports are not the same; if they are, the frame will be dropped, as it pertains to a destination on the same segment as the source. the destination address table entry is also inspected; for a forwarded frame, this must be a forwarding tag indicating a remote device as the target of the frame, or a hash bucket indicating a multicast, or will be non-existent (in which case the frame will be flooded, and must be sent across the pci bus to all remote devices). if a forwarding tag was located during the address lookup for the destination mac address, the remote hash bucket pointer is extracted from the srchashbkt field of the forwarding tag and placed in the hashbkt field of the data descriptor; otherwise, the source hash bucket pointer is placed in the hashbkt field. the frame has been successfully processed and classified; the source mac address statistics (i.e., the per-host statistics in the source hash bucket) and the per-port statistics are updated appropriately at this time. 7. the firmware now inspects the status of the dma controller increment channel, containing the hardware described in the previous section that supports pci data transfers. if the channel is not busy, then the information required to create a data descriptor is written into the control registers in the increment channel, together with a bitmask identifying the remote device(s) to which the frame is to be forwarded; the dma controller increment channel is then enabled. 8. the dma controller then writes out the data descriptor to the specified transfer ring(s) for each target device indicated by the bitmask in the previous step. after updating the transfer ring(s), the dma controller increments the appropriate request counter in the destination elan switch device via a pci memory write command to the address of the request counter. the data written to the counter is not significant, and is specified by a pair of internal registers set up at initialization time. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 121 9. the write to the request counter in the destination elan switch device automatically causes the request counter in the destination (i.e. remote) device to increment. this request counter increment causes, in turn, a request counter interrupt to be generated to the switch processor(s) in the remote device(s), notifying the switch processor of the presence of an outstanding frame transfer request. the switch processor(s) will then begin executing the request counter interrupt service routine firmware that is intended to handle these frame transfer requests. to reduce the amount of overhead involved in processing the request counter interrupt, the request counter hardware in the elan 1x100 implements an interlock that prevents the request counter interrupt from being asserted if the dma controller transmit channel is busy. this prevents needless busy-waiting by the switching firmware, as the first action of the request counter interrupt service routine is to set up the dma controller transmit channel to copy the ethernet frame across the pci bus. 10. the request counter interrupt service routine in each remote device will then set up the associated dma controller transmit channel to copy the element at the head of the appropriate transfer ring from the source device to the destination device. once the setup has been completed, the request counter interrupt service routine will decrement the request counter to remove the interrupting condition, and exit. 11. the dma controller transmit channel will first read the data descriptor contents out of the transfer ring, and then use the information in the data descriptor to locate the chain of packet buffers holding the ethernet frame and copy the packet buffer chain over the pci bus as well. the information in the copied data descriptor is placed into internal registers within the remote device for use by the switch processor firmware; the payloads of the packet buffers, however, are written directly into the 2048-byte internal transmit fifo in the remote device. note that the copy of packet buffers across the pci bus is only performed if the transmit fifo has space available to hold at least one maximum-length packet buffer payload (nominally 72 bytes). 12. the dma controller will read the data descriptor contents, as well as the entire linked-list of packet buffers (if any) over the pci bus in on continuous operation, as described in step 10. however, it will issue an interrupt to the switch processor immediately after the data descriptor as well as the 14-byte ethernet frame header have been read. this interrupt, which is referred to as the transmit header interrupt , is intended to allow the switch processor to begin the necessary processing to determine the disposition of the frame currently being transferred well in advance of the completion of the copy into the transmit fifo, thereby reducing or eliminating delays between transferring successive frames. the dma controller will continue to transfer the remainder of the frame data without stopping while the switch processor responds to the transmit header pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 122 interrupt and decides what must be done with the frame. in order to permit the switch processor firmware to determine the nature of the frame (and thus its ultimate fate), the dma controller loads the entire 16-byte data descriptor contents into eight 16-bit hardware registers that are accessible to the firmware. the information of interest to the firmware include the data descriptor flags field (which indicates whether the information being transferred represents a normal frame, a management frame, or a control/status message), the source device id and source port id, the hash bucket field, and so on. the firstpb and lastpb pointers are not relevant, as they are only necessary for locating the packet buffer chain in the source device's memory space. 13. the first action of the switch processor when executing the transmit header interrupt service routine is to read the data descriptor associated with the frame being transferred out of the hardware registers in the dma controller and to inspect the descriptor flags field. depending on the coding of the flags field, the transmit header interrupt service routine will perform the following actions: if the frame being transferred is a normal unicast ethernet frame, then the firmware will simply set up the frame to pass through the transmit fifo and ultimately be transmitted in the normal manner. if the frame being transferred is a normal broadcast or multicast ethernet frame, the firmware will check the learn bit in the flags field of the data descriptor to determine whether the frame contains a new source mac address. if the learn bit is set, then the firmware will verify that the source mac address is not already present (by checking the results of the hash lookup performed by the dma controller on the source mac address). if the mac address is not represented by an entry in the address table, it will create a forwarding tag for the mac address, with the srchashbkt field of the forwarding tag being set up from the hashbkt field of the data descriptor and the 48-bit mac address in the forwarding tag being obtained from internall hardware registers maintained by the dma controller. if the data being transferred is a message or a management frame, this will be indicated by the special bit in the data descriptor flags field being set. in this case, the firmware will have to wait until the entire frame or message has been read into the transmit fifo, and then perform a software copy of the frame or message payload into buffers in external sram. the firmware thus sets the dma controller up to continue normal processing until the frame has reached the head of the transmit fifo (as described below), and then interrupt the switch processor. the service routine for the latter interrupt will be actually responsible for copying the data out of the fifo: it will allocate the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 123 necessary quantity of free packet buffers, plus a free message descriptor to point to these packet buffers, copy the data out of the transmit fifo into the free packet buffers, and queue the entire message for background processing using the free message descriptor. this two-stage method of retrieving messages or management frames is adopted principally because messages and management frames are much rarer than normal unicast and multicast frames. for highest throughput, therefore, the normal frames should be switched with maximum efficiency, while management frames and messages can tolerate a slight loss of efficiency during processing. in many cases, the entire contents of a message may fit completely within the fields of a data descriptor. in this case, no packet buffers will be attached to the data descriptor; the transmit header interrupt will simply allocate a message descriptor from the free message descriptor pool and copy the contents of the data descriptor out of the hardware registers into the newly allocated message descriptor, which will be queued for background processing. as described in detail in a previous section, the dma controller also contains another hardware mechanism, called the disposition fifo , that improves the efficiency of the switching firmware when handling transmit frames. each of the 16 entries in this fifo corresponds to a frame that has been placed into the 2048-byte transmit fifo, and indicates how that frame is to be dealt with by the dma controller when it reaches the head of the transmit fifo. three possible actions may be requested by the firmware via codes written into the disposition fifo: send , drop , and stop . the expected uses of these codes are as follows: a send is written into the disposition fifo if the frame should be sent over the mac port when it reaches the head of the transmit fifo. this is the normal mode of operation, used for dealing with frames that should be transmitted without special processing. this is the typical action performed when the data descriptor flags field does not have the special bit set, thus indicating that no special processing needs to be performed for the frame. a stop is used by the transmit header interrupt service routine when it detects that the special bit in the data descriptor flags field is set, and the message-specific type code indicates a control/status message, or a management frame that was received from some other port and passed to this elan 1x100 device for special handling. the latter situation occurs only if this elan 1x100 is the master device in the system, and hence responsible for processing management and pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 124 spanning tree frames. when the first byte of the frame or message reaches the head of the transmit fifo, the dma controller will stop reading any more data out of the transmit fifo, and interrupt the switch processor with a stop interrupt , indicating that the message or management frame is ready to be read out of the transmit fifo. the switch processor firmware will then read the necessary data out of the transmit fifo; when the firmware processing is done, the disposition fifo entry may be either changed to a drop code to delete the frame from the transmit fifo (in the case of a control/status message or an snmp management pdu), or to a send code to transmit the frame over the mac port in the normal manner (typically in the case of broadcast control messages such as arp or icmp). an entry in the disposition fifo is set to a drop code to indicate that the frame can be simply deleted from the transmit fifo without transmitting it over the mac port. this is normally used in conjunction with the stop code; the transmit header interrupt firmware writes the stop code into the disposition fifo, and the stop interrupt service routine later changes this code to drop after the frame or message reaches the head of the fifo and has been read out by the switch processor firmware. 14. if the frame is a normal unicast, then it is necessary to update rmon host statistics pertaining to the transmission of the frame to the target host. however, it is possible that errors during transmission (late or excess collisions in half- duplex mode) can result in the transmission terminating in failure; this is not known until the transmission attempt is actually completed. to facilitate the proper update of rmon statistics, therefore, the firmware maintains a small ring buffer of entries referred to as the distribution fifo . this fifo (which is handled entirely by software) holds pointers to hash buckets in the address table of the elan 1x100 that correspond to the destination mac addresses contained within the frames stored within the main transmit fifo. when the transmit header interrupt service routine determines that the frame being transferred across the pci bus is a normal unicast, it places an entry into the tail of the distribution fifo that contains the hashbkt field of the data descriptor for the frame. when the transmission attempts for that frame have been completed, the entry for the frame (which will be at the head of the distribution fifo) will be read out and used to update the indicated hash bucket with the proper statistics. at this step, therefore, the firmware places an entry into the distribution fifo corresponding to the frame being processed. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 125 15. when the frame data has been completely read into the transmit fifo by the destination elan 1x100, the dma controller will automatically send an acknowledge back to the source device, notifying it that the data copy is complete and the memory resources used in the source device may be freed. this is done by initiating a single-word pci write transaction to the proper acknowledge counter in the source device; in a manner identical to request counters, the acknowledge counter in the source device will automatically increment when a write is performed to its assigned pci address. once the acknowledge counter in the source has been incremented, the transfer handshake is complete; the destination and source devices will autonomously perform the necessary final processing required to transmit the frame and free the resources, respectively. 16. the acknowledge counter increment performed by the dma controller in the destination device to the source device in the preceding step will generate an acknowledge counter interrupt to the switch processor in the source device. the switch processor will then execute the acknowledge counter interrupt service routine, which will first verify that the acknowledge notification was valid (i.e., at least one frame was queued for transfer to the destination device making the notification). if the acknowledge was expected, the firmware will then remove the entry at the head of the transfer ring for the destination device, updating the corresponding expansion port descriptor device accordingly. if the transfer ring entry indicates a unicast frame, the packet buffer chain for the frame is immediately freed (returned to the free packet buffer pool); if a multicast or broadcast is indicated, then the reference count field (refcount) in the last packet buffer is decremented first, and the packet buffer chain is only freed if the reference count goes to zero. if the packet buffer chain is freed, the maxbuffers field in the original source local port descriptor is incremented by the count of buffers freed, to permit the free buffers to be re-used for future received traffic. the firmware also notifies the dma controller that an entry in the transmit ring has been freed; the dma controller adjusts its internal pointer registers to take this into account. 17. the dma controller constantly reads data out of the head of the transmit fifo and passes them to the mac logic for transmission on the medium. when the frame that was transferred in steps 11 through 15 reaches the head of the transmit fifo, then it will check the disposition fifo entry for that frame. if the fifo entry indicates a send code, the dma controller will read the frame data out of the transmit fifo and present them to the mac logic. the mac logic will initiate frame transmission over the medium according to the ieee 802.3u specification, beginning with the preamble and sfd and ending with the 4-byte crc field. the mac logic is completely responsible for inserting any required interframe gap, counting off backoff intervals for half-duplex, and regulating the data rate; the dma controller simply reads data out of the transmit fifo and pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 126 presents them to the mac logic whenever the mac logic is ready to accept data. this process continues until the end of the current frame (as indicated by an end-of-frame delimiter being read out of the transmit fifo) has been reached. at this point, the dma controller notifies the mac logic that no more data are available for this frame. 18. after all of the data for the frame have been transferred to the external phy device (effectively terminating frame transmission), the dma controller asserts a transmit done interrupt to the switch processor. the functions of the dma controller in the destination device with regard to frame processing will be completed at this point. 19. in response to the transmit done interrupt, the switch processor invokes the transmit done interrupt service routine: the primary function of this routine is to update the per-port and per-host statistics based on the final transmit status. the per-port statistics are held in the local port descriptor data structure (as well as error counters in the port descriptor counter structure), and are updated for all transmission attempts of any type of frame. the per-host statistics reside in the hash bucket corresponding to the mac address, and hence these are updated only for successful transmissions of unicast frames. the hash bucket to be updated is indicated by the head entry in the distribution fifo. the count of octets transmitted for the current frame is supplied by the dma controller via a hardware register, and is used for updating the octet-level statistics counters for both the port and host statistics. it should be noted that the dma controller will not wait for the transmit done interrupt to be serviced before proceeding to the next frame in the transmit fifo. if the transmit done interrupt for a given frame is not serviced before the next frame completes transmission, however, the dma controller will halt the transmission of more frames from the transmit fifo until the switch processor executes the transmit done interrupt service routine. if the mac port is operating in half duplex mode, and a collision is sensed (i.e., the mii col signal is asserted) during the transmission of a frame, the mac logic immediately stops further data transmission for that frame and performs the standard ieee 802.3 collision jam and backoff sequence. on the completion of the jam, a collision interrupt is asserted to the switch processor, which then executes the collision interrupt service handler to perform the remainder of the ieee 802.3 collision functions in firmware. the sequence of operations performed by the collision interrupt handler is as follows: 1. the firmware first increments the count of collisions experienced by this frame; this count is maintained in the numcollide field in the local port descriptor, and tracks the number of transmit attempts made for a particular frame that ended in collision. the numcollide field is always zero prior to starting the first transmit attempt for each frame. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 127 2. if the incremented numcollide field is 16 (indicating that sixteen consecutive collisions occurred for the given frame), then the ethernet frame is discarded. this is done by setting the head entry in the disposition fifo to the drop code; the dma controller will automatically purge the frame from the transmit fifo, and proceed to the next one. otherwise, the head entry in the disposition fifo is left untouched (i.e., it will be a send code), and another transmission attempt will be made after the backoff period times out. 3. the backoff counter reload register in the mac logic is then set with a new random backoff value, computed according to the ieee 802.3 truncated binary exponential backoff algorithm. note that the backoff counter reload register is always set in advance with the next backoff timer to use on the next collision; thus it is loaded before beginning the first transmit attempt for a frame with the backoff value to use for the first collision; successively loaded with random values drawn from a greater and greater range until the fifteenth collision; as the sixteenth collision will cause the frame to be discarded, it is reset back to the minimum range backoff value prior to beginning the sixteenth transmission attempt. (this mechanism is employed to make the collision backoff times insensitive to the latency incurred by the switch processor firmware in setting up the backoff counter reload register.) broadcast and multicast frames are handled in essentially the same manner as unicast frames when performing device-to-device transfers, with the primary difference being that steps 9 through 18 are repeated by each destination device to transfer multiple copies of the data descriptor and packet buffers belonging to the frame across the pci bus. the source elan 1x100 consults its broadcast restriction mask, set up statically at configuration time or dynamically by the spanning tree algorithm, to determine the specific external devices to which the frame may be broadcast. it then queues the same frame for transmission on all of the required expansion port transmit frame queues (using multiple data descriptors, but without copying the packet buffers holding the actual frame data). note that a frame is copied to a destination device only once, regardless of the number of ports on the destination on which the frame is to be ultimately transmitted; the destination is responsible for replicating the frame to the target transmit ports. address learning and aging under normal circumstances, the elan 1x100 device acts as a transparent learning bridge, automatically learning new mac addresses seen in ethernet frames and associating them with actual physical ports. address learning is carried out in-line with frame switching whenever a new source mac address is encountered. the presence of a new source mac address is indicated by the failure of the hash lookup mechanism to return a hash bucket (or forwarding tag) for a source address lookup. at this point, the elan 1x100 switch processor will execute the address learning process. if multiple devices are present in the system, learned addresses will be propagated to all of them pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 128 by means of a simple protocol. all address learning functions are implemented in firmware running on the switch processor. note that only source mac addresses are ever learned by the elan 1x100. address learning in a multi-device elan-compatible system takes two steps: local address learning, by the device that received the frame containing the new source mac address; and remote address learning, by all of the other devices in the system, if any. local address learning address learning within the elan 1x100 device that first encountered the new source address takes the following steps: 1. the switch processor inspects the results of the source hash bucket search performed by the hash lookup mechanism and determines that it has failed, indicating that the source mac address is not present in the system. 2. the switch processor then checks the global address-learning-enable flag (a variable in the switch processor operating environment) to verify that address learning is enabled. if this flag is clear, indicating that address learning is disabled, the switch processor does not attempt to learn the source address, but simply skips to step 7. otherwise, the switch processor proceeds to step 3. 3. the address table limit counter (another variable in the switch processor operating environment) is now checked to determine whether the address table is full, i.e., the pre-configured maximum number of addresses have been learned. if the limit is zero, indicating that the address table is full and no more addresses can be learned, the switch processor cannot learn the new source address; it skips to step 7. 4. the switch processor has determined that address learning is enabled and possible. it now allocates an empty hash bucket from the free hash bucket pool and fills in the new source mac address and the pointer to the source local port descriptor into the macaddr and lpdptr fields, respectively, of the blank hash bucket. the remainder of the statistics and flags fields will have been set up already when the blank hash bucket was placed in the free pool, either by the initialization process or by the aging process. the switch processor then updates the timestamp field in the hash bucket. 5. the hash bucket must now be inserted into the hash table at the proper location. to do this, the switch processor computes the address of the appropriate entry within the hash pointer array. it then copies the contents of the 24 lsbs of this entry into the nexthb field of the newly created hash bucket, and writes the memory address of the hash bucket into the entry into the hash pointer array. this completes the insertion of the hash bucket into the linked-list of hash buckets pointed to by the hash pointer array entry. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 129 6. once the mac address has been learned by the elan 1x100, all of the other devices in the system must be notified of the existence of the new address so that they can learn the new address as well (by means of the remote address learning mechanism). this is done quite simply by forcing a broadcast of the ethernet frame, regardless of whether the frame was a unicast or broadcast, and setting the learn bit in the data descriptor corresponding to the frame. the switch processor thus sets the learn bit in the flags field of the data descriptor, writes the memory address of the newly learned hash bucket into the hashbkt field in the descriptor, and invokes the normal frame broadcast process to direct the frame to all of the remote devices in the. this completes the local address learning procedure. 7. if the mac address cannot be learned by the elan 1x100 due to lack of resources, the switch processor instead uses a pointer to a default hash bucket in place of the source hash bucket pointer in the data descriptor, and does not perform the remote address learning procedure. the remainder of the processing for the frame follows the normal switching requirements. as the mac address has not been learned, subsequent frames received by the elan 1x100 that are directed towards this mac address will always be flooded. when the local learning process is complete, the source mac address will have been represented by a new hash bucket in the address table (assuming that the learning was successful). the remainder of the frame processing is unchanged. remote learning process in a multi-device system, it is necessary for all devices in the system to maintain a consistent view of the address table, in order to properly forward frames between devices in an efficient manner. thus a learning process must be followed by all of the remote devices in the system when a local elan 1x100 signals that it has encountered (and learned) a new source mac address. the remote learning process is triggered whenever a data descriptor corresponding to an ethernet frame transferred over the pci bus is found to have the learn bit set in its flags field, and results in a forwarding tag for the mac address being placed into the address table. the remote learning process takes the following steps: 1. the switch processor checks the flags field of the data descriptor copied from the remote device (the source of the ethernet frame transferred across the pci bus) to see if the learn bit is set and the frame is a broadcast. if the learn bit is not set, the switch processor does not perform any address learning, but simply processes the frame in the normal manner. 2. the switch processor then checks the global address-learning-enable flag: if this flag is clear, indicating that address learning is disabled, the switch pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 130 processor declares an error, as the remote device should not have attempted to learn the mac address. otherwise, it goes to step 3. 3. the address table limit counter is now checked to determine whether the maximum number of addresses have been learned. if the counter is zero, the address table is full: the switch processor skips the complete remote learning process and simply goes on to process the frame in the normal manner. otherwise, it proceeds to step 4. 4. remote address learning has been determined to be possible. the switch processor allocates an empty 16-byte memory block from the free forwarding tag pool and formats it. it writes the new source mac address (read from the ieee 802.3 source address field of the ethernet frame), the pointer to the master hash bucket in the remote device (read from the hashbkt field of the data descriptor), and the chip number (obtained from the srcchip field of the data descriptor) into the macaddr, srchashbkt, and chipnum fields, respectively, of the blank forwarding tag. in addition, it fills in the ftflags field of the forwarding tag with the default value. 5. the forwarding tag must now be inserted into the hash table at the correct point. to do this, the switch processor hashes the mac address and computes the index into the hash pointer array (in the same manner as implemented by the hash lookup mechanism). it then converts the index into the actual address of the appropriate entry within the hash pointer array, reads the 24 lsbs of this entry, and writes the 24 lsbs into the nextft field of the newly created forwarding tag. finally, it writes the memory address of the forwarding tag into the hash pointer array, which completes the insertion of the forwarding tag into the address table. 6. the creation and insertion of the forwarding tag, carrying with it the necessary information required to direct frames targeted at the given mac address to the remote device, completes the remote learning process. the switch processor now continues with the rest of the frame switching process. note that the number of forwarding tags created within any of the elan 1x100 devices in a system must equal the sum of the numbers of hash buckets created in all of the other devices in the system (each new hash bucket created within any remote device results in a forwarding tag being created within this device). in addition, the sum of the forwarding tags and the hash buckets created by any one device cannot exceed the pre-set maximum number of addresses that can be learned by the system. default hash bucket a special mechanism is implemented to deal with the case when a new source mac address cannot be learned due to some reason (e.g., when the pool of available hash buckets is exhausted). this mechanism is necessary as the source hash bucket pointer pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 131 that is used at various points during the switching process must always point to a valid hash bucket data structure, as this pointer is utilized by the switching firmware to update statistics and so on. in addition, the local port descriptor pointer within the hash bucket must also be valid, and pointing to the correct local port descriptor corresponding to the physical port upon which the frame arrived. to deal with the above case, the initialization process creates one dummy (default) hash bucket within the switch processor operating environment at system start-up. this hash bucket is set up to correspond to the single physical port of the elan 1x100. this invalid hash bucket is not placed into the address table, and its mac address field is invalid. the dummy hash bucket will never be found by the hash lookup mechanism during the source and destination mac address resolution process. when a particular source mac address is not found in the address table, and cannot be learned due to some constraint, the switch processor instead sets up the source hash bucket pointer placed into the data descriptor to point to the default hash bucket. this source hash bucket pointer hence indicates a valid hash bucket (even though it is one with the wrong mac address, and invalid statistics fields); thus the remainder of the switching and frame forwarding firmware will continue to operate as normal. statistics updates may be done to the default hash bucket; as the statistics fields within the hash bucket are invalid anyway, these statistics updates will be irrelevant. in this manner, the switch processor can ensure that the source hash bucket pointer passed to the remainder of the system will always point to a valid hash bucket, even if learning is disabled or not possible. address aging process to reclaim the address table resources that have been allocated to network entities that are currently inactive or non-existent, the elan 1x100 implements an automatic address table aging mechanism. in essence, this mechanism causes a given address table entry to be deleted if a frame has not been received from the corresponding host computer (or other originator of traffic) for a specified period of time. the mechanism also implements a means whereby a topology change in the network (i.e., the movement of one or more hosts between ports on different elan 1x100 devices) can result in the removal of the outdated address table entry or entries and the substitution of new ones to reflect the new state of the network. in general, aging is carried out using the receivetimestamp field in the hash bucket data structures. this field is updated with an absolute time in microseconds by the switch processor whenever a valid frame has been received from the corresponding source entity. the receivetimestamp field thus indicates the last time at which the source was active. the aging process periodically scans the entire address table, comparing the receivetimestamp fields in the various hash buckets with the current value of the real-time clock; if the difference exceeds a pre-set threshold, then the hash bucket is removed and returned to the free hash bucket pool. in a system containing pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 132 more than one elan switch device, an additional process is followed to ensure that the forwarding tags on all of the other elan devices corresponding to the deleted hash bucket are removed before the hash bucket is itself eliminated. this is necessary to prevent system corruption due to inconsistent data structures. the normal aging time used by the elan 1x100 is set by the maxage variable, and may vary between 2 and 1 million seconds, with a default of 300 seconds. this aging time is used when there are no topology changes, and hash buckets are removed after their corresponding source entities have been silent for the time specified by maxage. if a topology change occurs, however, the aging time is set by the forwarddelay variable, which may also range between 2 and 1 million seconds, but defaults to 2 seconds. the purpose of the forwarddelay time is to quickly remove all inactive hash buckets without forcing the entire table to be purged, allowing the outdated address table entries resulting from the topology change to be replaced by the new ones. this mechanism has the benefit that mac addresses from which heavy traffic is being received (but have not shifted physical ports) will remain untouched in the address table, while at the same time the altered state of the network will be rapidly re-learned. the net result is intended to minimize the impact of topology changes in a busy network. note that this process is also aimed at permitting simple implementation of the ieee 802.1d standard. in some situations, it may be necessary to 'lock' certain address table entries permanently into the address table (i.e., to partially defeat aging without completely turning it off). each hash bucket contains a flag (referred to as the noage flag) that may be set; if set, the aging process will be prevented from removing the hash bucket or its associated forwarding tags, if any. note that the receivetimestamp field within the hash bucket will still be updated whenever a frame is received with the corresponding source address. three main components make up the aging process: 1. the receive interrupt service routine that performs the primary frame dispatching tasks is responsible for updating the receivetimestamp field in the source hash bucket whenever a frame is received from the corresponding source. the receive / interrupt service routine also notices when a mismatch occurs between the physical port indicated by the source hash bucket and the actual physical port on which the frame arrived, and flags a topology change notification to cause the address table to be updated. 2. a background scanning task is implemented to periodically check the receivetimestamp fields in all the hash buckets and purge any that have been aged out (i.e., whose source entities have not been active for some time). the background scanning task is also responsible for notifying the remainder of the chips in a multi-device system when a hash bucket must be removed, to allow the other chips to delete the corresponding forwarding tags. the notification is pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 133 performed via a special message (called an aging message) sent to the other chips. 3. a special routine, invoked whenever an aging message is received from another device in the system, that actually removes the forwarding tag referenced by the message. 4. of the three components, the first has already been described in the sections dealing with frame switching and inter-device frame transfers (see above). the other two will be described in detail in this section. background scanning task the background scanning task is invoked periodically (during idle periods, when frame switching is not occurring) to search the entire address table for hash buckets that need to be removed. the scan period is configurable, and defaults to 1 second. the first step executed by the background scanning task is to determine the limit imposed on the age of hash buckets. if a topology change was not detected, this limit is simply the contents of the maxage variable. if, however, a topology change occurs, this limit is set to the contents of the forwarddelay variable for a period equal to the forwarddelay time, after which it reverts to the maxage time. thus, for example, if the default values of 300 seconds and 2 seconds, respectively, are used for maxage and forwarddelay, then for the 2 seconds following a topology change the age limit is set to 2 seconds, after which the age limit is set to 300 seconds. after the limit has been set, the 48-bit internal real-time clock is read and preserved as the current time against which the receivetimestamp fields in the hash buckets will be compared. the next step is to scan the address table. to implement this, the hash pointer array is simply scanned linearly, starting at the first pointer and terminating at the last. if any pointer is found to be non-null, this indicates that a list of one or more hash buckets and/or forwarding tags is attached to that entry; the list is then sequentially scanned until no more elements remain in the list, after which the scanning returns to the next hash pointer array entry. after the last entry in the hash pointer array has been checked, the background scanning task returns. for each hash bucket or forwarding tag found, the flags field is checked to determine whether it is a hash bucket, and also whether it can be aged out. if so, the receivetimestamp field of the hash bucket is read and subtracted from the current time to give the age of the hash bucket, and the result is compared to the age limit. if the comparison fails (i.e., the age of the hash bucket is greater than the limit), then the hash bucket is removed from the linked list; otherwise, the hash bucket is left untouched and scanning proceeds. once a hash bucket that has aged out has been located and removed from the address table, it must be freed. this is not done immediately, however, as there may be other pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 134 devices in the system with forwarding tags that reference this hash bucket; if the hash bucket is destroyed before deleting these forwarding tags, then incoming frames on other devices that are directed to the corresponding mac address may cause inconsistencies and failures. instead, all of the hash buckets that have been removed from the address table are placed on a separate linked list (referred to as the pending free hash bucket list). in a multi-device system, a notification message is sent to all other devices in the system for each hash bucket placed on this list, requesting that any forwarding tags corresponding to the hash bucket be removed. to avoid the complexity of a request/acknowledge protocol, the pending free hash bucket list is simply maintained for a short time (1 second), which gives the other devices ample time to receive the notification message and remove the specified forwarding tags from their address tables. following this time, the entire pending free hash bucket list is deleted and the hash buckets returned to the free hash bucket pool. the format of a notification message is given in the following subsection. forwarding tag removal task the forwarding tags corresponding to a removed hash bucket must also be removed from the system, otherwise system errors can occur due to transferred frames referencing inconsistent address tables. the removal of forwarding tags is triggered by the notification messages sent out whenever hash buckets are aged out by any device in the system. the format of the notification message follows that of a standard data descriptor, but with null firstpb and lastpb pointers, and a special flags field, as given below: 31 24 23 16 15 8 7 0 byte offset flags nextdd 0 unused 0x000000 4 unused hashindex 8 unused hashbktaddr 12 nextdd: 24-bit pointer to next data descriptor in linked-list of data descriptors. flags: 8-bit data descriptor flags field, formatted as below. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 135 hashindex: 16-bit index of hash pointer array at which the hash bucket (and forwarding tags) may be found. hashbktaddr: 24-bit pointer to hash bucket being removed. the nextdd field is set up properly when the message descriptor is queued. the flags field is formatted as shown below: 76543210 01000100 the encoding of the flags field indicates that this is a message descriptor that is notifying the recipient of the need to delete the forwarding tag corresponding to an aged-out hash bucket. the hashindex and hashbktaddr fields are expected to be used by the recipient in locating the forwarding tag that must be removed. the hashindex field is simply the index of the hash pointer array at which the hash bucket itself is located, which will be identical to the index at which the forwarding tag will be located in the remote device. the hashbktaddr value is the 24-bit address of the hash bucket being deleted, and will be compared to the corresponding field in the forwarding tag to ensure that the correct forwarding tag will be removed. the notification messages described above are treated as standard data descriptors and transferred to the remote device by the owner of the hash bucket using the normal pci expansion port transfer protocol (with the exception that no packet buffers are transferred, as the firstpb pointers in the message descriptors are null). upon receipt of a notification message, a remote device (elan 1x100 or other) must access its own address table, locate the proper forwarding tag using the data specified in the message, and remove and deallocate the forwarding tag. buffer and queue management the switch processor implements all of the buffer and queue management in an elan 1x100 device, using mechanisms implemented as firmware routines. buffer management is carried out by means of a port buffer allocation limit, plus a global broadcast frame limit that prevents excessive use of system resources by high levels of broadcasts. queue management (on the transmit queues) is performed via a background task that periodically monitors the different transmit queues and handles housekeeping tasks as required. in addition, broadcast rate limiting is implemented to avoid system overload during broadcast storms or other malfunctions. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 136 all of the parameters associated with the buffer and queue management functions implemented by the elan 1x100 device are configurable by means of system variables. these variables may be set statically to default values at boot time, or altered during normal system operation as required. buffer management as already mentioned, two forms of buffer management are performed by the elan 1x100 device. the first mechanism attempts to control the number of receive frames that are accepted for queueing to ensure that in no case will the buffering capacity of the system be exceeded (i.e., the dma controller will never run out of free packet buffers). the second mechanism places a limit on the number of broadcast or multicast frames that will be buffered by the system at any one time; this limit prevents unicast traffic from being unfairly affected due overconsumption of system resources by large amounts of broadcasts or multicasts. port buffer allocation limits the first level of buffer allocation control uses the 16-bit maxbuffers field in the local port descriptor structure. this field is set up at initialization time with the maximum number of (fixed-size) packet buffers that the mac port is allowed to consume. whenever a valid frame is received on the mac channel, the switch processor firmware subtracts the number of packet buffers required to hold the frame from the maxbuffers field in the local port descriptor. if the result is less than or equal to zero, it indicates that insufficient buffer capacity is available to hold the frame; the frame is then discarded. if the result is greater than zero, the frame is accepted, and the maxbuffers field is updated to reflect this fact. the maxbuffers field is subsequently incremented (again, by the number of packet buffers used to contain the frame data) when the frame is transferred to another device across the pci bus or processed and discarded. the permissible range of the maxbuffers fields is between 44 and 32767, depending on the available packet buffer memory. this buffer allocation limit guarantees that the dma controller will not run out of buffers in the free packet buffer pool. if the backpen bit is set in the portflags field of a local port descriptor, and a high traffic condition causes its maxbuffers field to become less than or equal to zero, then backpressure flow control will be started for that port. in this case, the switch processor firmware will enable the mac channel to either begin jamming the medium by continuously transmitting a bit pattern in half-duplex mode, or to send a flow control frame in full-duplex mode. note that the maxbuffers variable in the local port descriptor is maintained by the switch processor firmware in cached data space, and thus cannot be updated by direct access over the pci bus interface. instead, the messaging interface must be used to modify this variable during system operation, if desired. this function is tbd. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 137 broadcast frame limit broadcast and multicast frames consume a considerable amount of memory resources of an elan 1x100 system for a potentially long time. if, for example, a port is receiving a high rate of broadcasts, then the broadcast frames (which must be sent out over all the other devices in the system) may have to be buffered for a long time, and will also require a large number of entries in the transfer rings in order to be transferred to all of the other elan switch devices. a programmable broadcast frame limit is therefore provided to permit the system implementer to exercise some control over the amount of system resources that may be consumed by broadcast and multicast traffic. the broadcast/multicast frame limit is implemented by the switch processor firmware using a single global maxbcstframes variable in the cached data space. this variable is set up initially to the maximum number of broadcast frames permitted to be buffered by the elan 1x100 device. whenever a newly received broadcast or multicast frame is detected by the switching code executed by the switch processor, the maxbcstframes variable is decremented by 1; if the result is equal to or less than zero, the broadcast or multicast frame is discarded, as the broadcast frame limit has been exceeded. if the result is greater than zero, the broadcast/multicast frame is accepted for processing in the usual manner (i.e., queued to the target expansion port queues), and the maxbcstframes variable is updated accordingly. whenever a broadcast or multicast frame has been completely transmitted or transferred, i.e., the packet buffer chain holding the broadcast or multicast frame has been returned to the free packet buffer pool, the maxbcstframes variable is incremented, allowing additional broadcast or multicast frames to be accepted. note that the broadcast/multicast frame limit is applicable to frames received over the pci expansion port, as well as frames received over local mac ports. the maxbcstframes variable is maintained by the switch processor firmware in cached data space, and is hence not accessible directly over the pci bus interface. the messaging interface must be used to update it. this operation is tbd. transmit fifo management the elan 1x100 implements a mechanism to monitor the transmit fifo to ensure that frames do not persist in the transmit fifo for too long before being transmitted. this can happen if the medium associated with the mac channel is continually busy due to a malfunctioning system or a jabbering upstream host or switch, or if some hardware fault is present that prevents frames from being transmitted. in this case, it is possible that the transmit fifo will fill up with one or more frames that will never be sent out, blocking the corresponding transfer queues in the source devices that need to pass frames out the elan 1x100 mac port. in extreme cases, the entire buffering in the system can ultimately be consumed by these blocked frames, bringing the system to a halt. to detect such a condition, the elan 1x100 switch processor implements a two- pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 138 stage procedure to determine whether a transmit fifo has been blocked for a long time. the first part of the procedure is implemented by the transmit header interrupt service routine, that is invoked whenever the header of a frame has been read into the transmit fifo. this routine writes the contents of the clock register pair in the switch processor, which implements the real-time clock, into the lasttransmit memory variable as part of its processing. the lasttransmit variable thus records the last time that a frame was read into the transmit fifo. the second portion of the transmit fifo management process is a background task that is periodically invoked when the switch processor is idle. this background task checks the current status of the request counters implemented by the elan 1x100 for the pci transfer handshake. if any of the request counters is non-zero, it indicates that one or more frames are pending to be transmitted out the elan 1x100 mac port. in this case, the background task subtracts the contents of lasttransmit variable from the current value of the clock register pair; if the difference is greater than a pre-set threshold, this indicates that the transmit fifo has been blocked for a considerable amount of time, and a system malfunction has occurred. in this case, the transmit fifo management process will attempt to clear out the frames from the transmit fifo (by setting their disposition fifo entries to drop ) to advance the transfer queues in the source devices and thereby reclaim the buffer resources. the threshold determining the maximum time that the transmit fifo is permitted to be blocked is a configurable parameter. the default value for this threshold is 1 second. broadcast rate limiting it is desirable to provide some form of limit on the rate of throughput of broadcasts handled by an elan 1x100 system; this limit should be set to allow a relatively small, 'normal' level of broadcasts, but prevent the excessive rates of broadcasts that can occur during malfunctions such as broadcast storms. it should be noted that the rate at which broadcasts occur (not the total number of broadcasts being handled by the system) must be limited; the limit is therefore set in terms of broadcast frames accepted and processed by the system per second. it should also be noted that multicasts are not subject to this limit. the elan 1x100 implements broadcast rate limiting via firmware running on the switch processor, using a combination of operations performed by the frame switching tasks coupled with a periodic background process. the broadcast rate limit is actually implemented by the 16-bit bcstrem variable in the switch processor firmware data space. bcstrem is initially set to a programmable value, defined by the 16-bit bcstlimit variable (which in turn is initialized to a default during system boot time, and which may be altered during system operation to modify the permissible broadcast rate). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 139 whenever a broadcast frame (i.e., one with the destination mac address set to all- ones) is being processed by the switching firmware, the switch processor decrements the bcstrem variable by 1 and checks the result. if the result is less than or equal to zero, the switch processor simply discards the frame, as the broadcast rate limit has been exceeded; otherwise, it updates the bcstrem variable with the decremented value, and accepts the broadcast frame for normal processing and eventual transmission. the bcstrem variable is never incremented by the switching firmware. hence, when it goes to zero, no more broadcast frames will be accepted by the elan 1x100 device. a background task is periodically executed every ten milliseconds by the elan 1x100 switch processor under timer control. the purpose of this background task is to reset the bcstrem variable to the contents of bcstlimit, thus permitting broadcasts to continue for the next ten millisecond period. the value of the bcstlimit variable is therefore directly equal to the number of broadcast frames that will be forwarded by the system every ten milliseconds. the bcstlimit variable may be set to any value between 0 and 32,767. setting this variable to 100, for example, results in a maximum average broadcast rate of 10,000 frames per second; setting it to zero shuts off broadcasts completely, while setting it to its maximum value (32,767) effectively removes the broadcast rate limiting feature. it should be noted that the broadcast rate limiting feature allows a short burst of broadcast every 10 milliseconds until the limit is reached, at which point all further broadcast frames are discarded. statistics collection the elan 1x100 device collects a number of snmp and rmon mib statistics during normal operation. these statistics are maintained in the local port descriptor, the port descriptor counter structure, and the hash buckets. some internal statistics are also held in the global memory area. the locations and sizes of the individual statistics counters are described in the sections above that deal with the various data structures. a summary of all of the statistics maintained by the elan 1x100 device, as well as the data structures in which they are located, is given in the following tables. note that all of the counters are 32 bits in size, and roll over (according to the snmp standard) when they are incremented beyond their maximum count. the counters maintained by the elan 1x100 device on a per-port basis are described in the following table: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 140 port counters name location description rxucstframes portdesc valid unicast frames received on this port rxucstoctets portdesc valid unicast octets received on this port rxbcstframes ctrblk valid broadcast frames received on this port rxbcstoctets ctrblk valid broadcast octets received on this port rxmcstframes ctrblk valid multicast frames received on this port rxmcstoctets ctrblk valid multicast octets received on this port rxfloodframes ctrblk valid frames received and then flooded to all ports rxfloodoctets ctrblk valid octets received and then flooded to all ports alignerrors ctrblk frames received on this port with alignment errors crcerrors ctrblk frames received on this port with crc errors dribbleerrors ctrblk frames received on this port with dribble bit errors longerrors ctrblk oversize frames received with good crcs 1 jabbererrors ctrblk oversize frames received with bad crcs shorterrors ctrblk undersize frames received with good crcs runterrors ctrblk undersize frames received with bad crc macerrors ctrblk frames lost due to internal mac/fifo errors droperrors ctrblk frames lost due to resource limits (out of buffers) rxerroroctets ctrblk errored octets received 2 rxframes64 portdesc 64-byte frames received (valid or errored) rxframes65 portdesc 65-127 byte frames received (valid or errored) rxframes128 portdesc 128-255 byte frames received (valid or errored) rxframes256 portdesc 256-511 byte frames received (valid or errored) rxframes512 portdesc 512-1023 byte frames received (valid or errored) rxframes1024 portdesc 1024-1518 byte frames received (valid or errored) txframes portdesc valid unicast frames transmitted out this port txoctets portdesc valid unicast octets transmitted out this port txdefers portdesc frames subject to deference on first transmit 1 the mac logic in the elan 1x100 truncates receive frames that are longer than the preset maximum frame length before the crc is computed. thus received frames larger than the preset maximum frame length will also cause a crc error, and hence oversize frames will actually be included in the jabbererrors counter and not the oversizeerrors counter. 2 due to the truncation of oversize frames, the count of octets received will not increase past one greater than the preset maximum frame size. thus frames that are larger than the preset maximum frame length will increment the rxerroroctets counter by exactly the one more than the preset maximum frame length, not the actual frame length. for example, if the maximum frame length is set to 1518 bytes, all oversize frames will increment the rxerroroctets counter by 1519, regardless of the actual number of bytes in the frame. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 141 txerrors ctrblk transmit frames lost due to internal errors singlecollide ctrblk frames transmitted after a single collision multcollide ctrblk frames transmitted after multiple collisions latecollide ctrblk frames discarded due to late collisions collideabort ctrblk frames discarded due to excessive collisions in the table above, note that "portdesc" refers to the local port descriptor structure, while "ctrblk" denotes the port descriptor counter structure. the per-port statistics maintained in the port descriptor counter structure may be retrieved at any time by direct access via the pci bus interface; however, the statistics in the port descriptor are cached by the switch processor, and hence can only be retrieved via the message interface. the elan 1x100 device also maintains counters on a per-mac-address (or per-host) basis, with a separate set of counters being maintained for each mac address that has been learned by the system. these counters are held in the hash bucket associated with the learned mac address. (note that forwarding tags do not contain any counters; hence only one set of counters will be maintained for each mac address in a multi- device system, rendering retrieval of the per-host statistics relatively straightforward.) these counters are described in the following table: per-host counters name description rxhucstframes valid unicast frames received from this host rxhbcstframes valid broadcast frames received from this host rxhmcstframes valid multicast frames received from this host rxhfloodframes valid frames received from this host and then flooded rxherrorframes errored frames received from this host rxhoctets octets received from this host, valid or invalid txhframes valid unicast frames transmitted to this host txhoctets valid unicast octets transmitted to this host lastrx (receivetimestamp) time at which frame was last received from this host createtime creation time of hash bucket the per-host statistics may be retrieved at any time via direct accesses to the hash buckets in the address table through the pci bus interface, or using the message interface. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 142 messaging protocol this section is tbd. spanning tree operation this section is tbd. rtos operation this section is tbd. udp/ip protocol stack operation this section is tbd. snmp operation this section is tbd. device interface via pci this section describes how external devices that are not elan 1x100s (or members of the elan family) may be interfaced to the elan 1x100 device via the pci bus. in general, such devices must follow the defined elan 1x100 messaging and frame transfer protocol for smooth operation. if the protocol is followed, then the external devices appear to the elan 1x100 chip as members of the elan family; they may then participate in all aspects of normal operation, including frame transfers, address learning and aging, messaging, and statistics gathering. frame transfer to non-elan devices this section is tbd. participation in address learning this section is tbd. participation in the messaging protocol this section is tbd. accessing variables and statistics this section is tbd. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 143 byte ordering the elan 1x100 internally uses a little-endian byte ordering scheme to store frames and data structures in local memory, and to transfer frames and communication messages across the little-endian pci bus. in this scheme, the least significant bit of any 32-bit data word appears on the least-significant bit of the memory and pci data buses, and is also placed within the least-significant byte address in memory. if less than four bytes are being transferred over a data bus, they are right-aligned on the bus, and placed in the memory in increasing address order. the ethernet standard, however, specifies a big-endian byte ordering scheme, which is the reverse of the ordering used by the elan 1x100 device. to properly align the various fields within a received ethernet frame for handling by the switch processor, therefore, the elan 1x100 performs a big-endian to little-endian conversion in the mac interface block during receive, and a little-endian to big-endian conversion during transmit. the following diagram illustrates the default mapping between an ethernet frame and packet buffers transmitted across the pci bus or stored in local memory: default byte ordering byte 0 01243567 byte 1 01243567 byte 2 01243567 byte 3 01243567 byte 4 01243567 byte 4 76543210 byte 3 byte 2 byte 1 byte 0 76543210 76543210 76543210 76543210 byte 7 byte 6 byte 5 76543210 76543210 76543210 increasing time increasing time ethernet/802.3 frame pci bus dwords nextpointer size ad31 ad0 unused count . . . ... pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 144 to permit interfacing of non-elan 1x100 devices via the pci bus, this byte ordering scheme may be selectively modified using the mwbe, mrbe, swbe, srbe and epbe byte swap enable bits in the host control register. the mwbe and mrbe bits control the pci bus master, and cause all data (payload and header information for packet buffers, as well as data descriptor contents) to be statically byte-swapped prior to writing them to or reading them from a pci bus slave (i.e., as a result of dma controller transfers). similarly, the swbe and srbe bits force the pci bus slave logic in the elan 1x100 to swap data words written to and read from internal registers and memory by an external master. finally, the epbe bit, if set, disables the big-endian to little-endian conversion performed on the ethernet frame information by the mac interfaces, without affecting the byte ordering of the rest of the data structures or the packet buffer headers. when the epbe bit is set, the alternate byte ordering scheme used is shown in the figure below (assuming that the mwbe, mrbe, swbe and srbe bits retain their default values): alternate byte ordering byte 0 01243567 byte 1 01243567 byte 2 01243567 byte 3 01243567 byte 4 01243567 . . . byte 0 byte 1 byte 2 byte 3 76543210 byte 7 76543210 76543210 76543210 76543210 byte 4 byte 5 byte 6 76543210 76543210 76543210 increasing time increasing time ethernet/802.3 frame pci bus dwords nextpointer size ad31 ad0 unused count ... pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 145 elan 1x100 / elan 8x10 expansion bus data transfer rates this section describes what the expected pci expansion bus utilization is as a function of the following system parameters: number of elan 1x100 chips in the system number of elan 8x10 chips in the system ethernet traffic patterns for the 10 mbit and 100 mbit links the pci bus utilization metric is then applied to determine if the switch configuration and traffic pattern will result in a blocking or non-blocking switch implementation. the data provided allows you to create your own spreadsheet to determine if the switch configuration and traffic mix that is required in your implementation can be supported. it is assumed for the sake of clarity that the traffic mix is sustained (i.e. steady state); since both the pm3350 and pm3351 implement store-and-forward switching with dynamically allocatable buffers you should get the same result if you take a statistical time average of the data traffic as opposed to an instantaneous frame rate such that the period of averaging is less than or equal to the time it would take to receive frames that would utilize 50% of the maximum allocatable number of packet buffers. since the pm3351 elan 1x100 is a 1-port device the limiting factor in constructing a switch using the chip is the bandwidth that can be supported over the pci expansion bus. the pci bus interface that is used on both the elan 1x100 and elan 8x10 devices together with the elan frame transfer protocol that is used results in a maximum sustainable throughput of 500 mbit/sec on the pci bus. a switch configuration and traffic mix that requires sustained throughput of l ess than 500 mbit/sec on the pci expansion bus will be non-blocking; a switch configuration and traffic mix corresponding to a sustained throughput of greater than 500 mbit/sec will result in a blocking ethernet switch configuration. the pm3351 and pm3350 chips, if used in a blocking configuration, will do one of two things: 1. if flow control is enabled, then flow control will be enabled until packetbuffers are returned to the free queue 2. if flow control is not enabled, then frames that are being received from the ethernet physical layer device will be dropped until there are a sufficient number of packetbuffers in the free pool in which to format the frame. the following derivation shows how the rate of traffic being received on the ethernet physical layer corresponds to the transfer rate as seen on the pci expansion bus. given: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 146 1. let mlp represent the percentage of frames that are received on the link media that require to be switched across the pci expansion bus. let mports represent the number of ports of the device: for the pm3350 this is 8, for the pm3351 it is-1. since the pm3351 is a 1-port device, each frame received on the 100 mbit link media is switched over the pci expansion bus so mlp is 1. however, the pm3350 is an 8-port device so not all unicast traffic may need to be switched across the pci bus; hence, mlp may be less than 1 in that case. 2. let mrfr be the relative frame rate. this is the ratio of the actual frame rate to the maximum ethernet frame rate. restating, this is the relative percentage of time that the link media is non-idle that does not include the standard interframe gap of 96 bit times. if you are modelling a network running at maximum ethernet frame rates, mrfr is 1. 3. let mdplx represent a per-port multiplier that is 0.5 for half duplex operation and 1.0 for full duplex operation. 4. let mpfsz represent a multiplier that represents the elan frame transfer protocol overhead with respect to the time it took for the frame to be sent on the link media (assuming a standard interframe gap of 96 bit times and nominal preamble length of 64 bits). mpfsz is a function of: the link rate (mpfsz is directly proportional to the link media rate). the ethernet framesize the size of the packetbuffer structure being used on the chip (default size is 80 bytes). example 4.1: calculation of mpfsz for a 64 bytes frame for a 100mbit link: link time = 96*10 (ifg) + 64*10 (preamble) + 64*8*10 (data) = 6720 ns bits required to have frame read across the pci bus by one chip: data descriptor = 16 bytes 1 request counter increment + 1 acknowledge counter increment = 8 bytes pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 147 1 packetbuffer = 80 bytes so mpfsz is (104 bytes * 8 bits/bytes) / 6720 ns = 0.124 bits/ns. example 4.2: calculation for a 64 bytes frame for a 10mbit link: this is simply 1/10 of the mpfsz for the 100 mbit example, or 0.0124 bits/ns a graph of mpfsz versus framesize is given is shown below. as can be seen from this figure, the worst case values of mplfsz is approximately 0.125 bits/ns for 100 mbit media (pm3351) and 0.0125 for 10 mbit media (pm3350). mpfsz(100mb) versus framesize given 80 byte packetbuffers framesize (bytes) mpfsz(100mb) 0.11 0.112 0.114 0.116 0.118 0.12 0.122 0.124 0.126 0 500 1000 1500 2000 5. let mdest be the number of chips in the system that will need to read the frame across the pci expansion bus utilizing the elan frame transfer protocol. for unicast frames, mdest is simply 1. for broadcast frames this is given by n-1 where n is the total number of switch chips connected to the pci expansion bus. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 148 whether the frame is unicast or broadcast/mulitcast over the pci expansion bus is a function of the destination address and whether the source and destination addresses have been learned. example #1: lets examine the worst-case pci expansion bus data rate for a 2 port -100 mb, 32-port 10 mb switch constructed using two pm3351 and four pm3350 chips assuming: all ports operating at maximum frame rate (mfr =1) all frames are switched over the pci bus (mlp = 1) the 100 mbit ports are full-duplex and the 10 mbit ports are half-duplex all of the 10 mbit traffic will be switched over the pci expansion bus (i.e. not switched to local ports on the elan 8x10 devices). the pci data transfer rate is therefore: {2*num_pm3351 * 1 (mlp) * 1 (mports) * 1 (mrfr) * 1 (mdplx) * 0.125 bits/ns (max mpfsz) * 1 (mdest for unicast)} + {3*num_pm3350 * 1 (mlp) * 8 (mports) * 1 (mrfr) * 0.5 (mdplx) * 0.0125 bits/ns (max mpfsz) * 1 (mdest for unicast)} = (0.25 bits/ns + 0.20 bits/ns) = 450 mbit/sec since this number is less than 500 mbit/sec the switch configuration will be non- blocking. example #2: lets examine the maximum sustainable broadcast frame for a 2 port -100 mb, 24-port 10 mb switch constructed using two pm3351 and three pm3350 chips assuming: the 100 mbit ports are full-duplex and the 10 mbit ports are half-duplex pci bus max transfer rate is 500 mbit/sec < {2*num_pm3351 * 1 (mlp) * 1 (mports) * 1 (mrfr_max_learn) * 1 (mdplx) * 0.125 bits/ns (max mpfsz) * 3 (mdest since three other chips in the system)} + {2*num_pm3350 * 1 (mlp) * 8 (mports) * 1 (mrfr_max_learn) * 0.5 (mdplx) * 0.0125 bits/ns (max mpfsz) * 3 (mdest since three other chips in the system)} pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 149 < mrfr_max_learn * {750 mbit/sec (received on 100 mbit links) + 300 mbit/sec (received on 10 mbit link)} solving for mrfr_max_learn gives: mrfr_max_learn = 500 mbit/s / (1050 mbit/s) = 0.47 so the pci expansion bus has a transfer rate adequate to support up to 47% of the frames received being broadcast to all chips in the system (this could include frames that are required to be learned). example #3: determine an equation that gives the maximum number of 100 mbit and 10 mbit ports that can be used with the pm3351 and pm3350 devices and still allows for a non- blocking switch implementation. given: all destination traffic is unicast all 100 mbit links operate in full duplex all 10 mbit links operate in half duplex pci bus max transfer rate is 500 mbit/sec: < (num_pm3351 * 125 mb/s) + (num_pm3350 * 8 * 0.5 * 12.5 mb/s) solving for num_pm3351 and num_pm3350 gives the results that are given in the table found in the description section of the datasheet. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 150 pci register/memory access the elan 1x100 pci configuration register space, the entire 16 mb local memory address space, plus a subset of the internal device registers, are visible via the pci interface. the device registers and memory may be accessed to configure the device, monitor status and perform packet buffer transfers. pci configuration space the 256 byte pci configuration register space implemented by the elan 1x100 is organized as 64 32-bit registers. only 19 of these are currently defined. sixteen registers (at byte addresses 0x00 to 0x3f) are used to implement the standard pci configuration space header; an additional 3 (at byte addresses 0x40 to 0x48) are used for bus error monitoring and recovery. pci configuration registers can only be accessed when the pci interface is a target and a configuration cycle is in progress as indicated using the idsel input. the format of the pci configuration register space supported by the elan 1x100 is given below: 31 0 byte addr. deviceid vendorid 0x00 status command 0x04 classcode revid 0x08 bist headertype latencytimer cachelinesiz 0x0c localmembase 0x10 reserved 0x14 . . . . . . reserved 0x2c expansionrombaseaddress 0x30 reserved 0x34 reserved 0x38 max_lat min_gnt interruptpin interruptline 0x3c 0x001b80 merror mrd maxburstlen 0x40 currmasterrdaddr 0x44 currmasterwraddr 0x48 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 151 notes on pci configuration register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. except where noted, all configuration bits that can be written into can also be read back. this allows the processor controlling the pm3351 to determine the programming state of the block. 3. writeable pci configuration register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only pci configuration register bit locations does not affect pm3351 operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the pm3351 operates as intended, reserved register bits must only be written with their default values. similarly, writing to reserved registers should be avoided. pci configuration registers pci configuration registers can only be accessed by the pci host. for each register description below, the hexadecimal register number indicates the pci offset. register 0x00: vendor identification/device identification bit type function default bit 31 to 16 r deviceid[15:0] 0x3351 bit 15 to 0 r vendorid[15:0] 0x11f8 vendorid[15:0]: the vendorid[15:0] bits identifies the manufacturer of the device, and contains the vendor id assigned to pmc-sierra by the pci sig. deviceid[15:0]: the deviceid[15:0] bits define the particular device, and is set to 0x3351 hexadecimal to indicate an elan 1x100 device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 152 register 0x04: command/status bit type function default bit 31 r/w dpe 0 bit 30 r/w sse 0 bit 29 r/w rma 0 bit 28 r/w rta 0 bit 27 r/w sta 0 bit 26 r dvtim[1] 0 bit 25 r dvtim[0] 1 bit 24 r/w dpr 0 bit 23 r fbcap 1 bit 22 to 16 r reserved 0x00 bit 15 to 10 r reserved 0x00 bit 9 r/w fben 0 bit 8 r/w seen 0 bit 7 r wcyc 0 bit 6 r/w peen 0 bit 5 r vps 0 bit 4 r mwlen 0 bit 3 r scen 0 bit 2 r/w men 0 bit 1 r/w msen 0 bit 0 r isen 0 the lower 16 bits of this register make up the command register which provides basic control over the pm3351's ability to respond to pci accesses. when a 0 is written to all bits in the command register, the pm3351 is logically disconnected from the pci bus for all accesses except configuration accesses. the upper 16-bits are used to record status information for pci bus related events. reads to the status portion of this register behave normally. writes are slightly different in that bits can be reset, but not set. a bit is reset whenever the register is written, and the data in the corresponding bit location is a 1. isen: the i/o space enable (isen) bit is hardwired to zero as the pm3351 does not implement i/o space. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 153 msen: when the memory space enable (msen) bit is set to one, the pm3351 will respond to pci bus memory accesses. clearing msen disables memory accesses. men: when the master enable (men) bit is set to one, the pm3351 can act as an master. clearing men disables the pm3351 from generating pci accesses. scen: the pm3351 does not decode pci special cycles. the scen bit is hardwired to 0. mwien: the pm3351 does not generate memory-write-and-invalidate commands. the mwien bit is hardwired to 0. vps: the pm3351 is not a vga device. the vps bit is hardwired to 0. peen: when the peen bit is set to one, the pm3351 can report parity errors. clearing the peen bit causes the pm3351 to ignore parity errors. wcyc: the pm3351 does not perform address and data stepping. the wcyc bit is hardwired to 0. seen: when the seen bit is set high, address parity errors result in the assertion of the serr* output. clearing the seen bit disables the serr* output. seen and peen must be set to report an address parity error. fben: if the fast back-to-back enable (fben) bit is set, the pm3351 bus master will attempt to do fast back-to-back cycles across the targets. fbcap: the fast back-to-back capable (fbcap) bit is hardwired to one to indicate the pm3351 supports fast back-to-back transactions with other targets. dpr: the data parity reported (dpr) bit is set high if the pm3351 has monitored or reported a data parity error to one of its transactions as a bus master and the peen bit is set. the dpr bit is cleared by the pci host. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 154 dvtim[1:0]: the devsel timing (dvtim) bits specify the allowable timings for the assertion of devsel* by the pm3351 as a target. these bits are hardwired to zeros as the pm3351 asserts devsel using fast (1-cycle) response timing. sta: the signaled target abort (sta) bit is hardwired to zero because the pm3351 will never generate a target abort during a slave access cycle. rta: the received target abort (rta) bit is set high by the pm3351 when as an initiator, its transaction is terminated by a target abort. the rta bit is cleared by the pci host. rma: the received master abort (rma) bit is set high by the pm3351 when as an initiator, its transaction is terminated by a master abort. the rma bit is cleared by the pci host. sse: the signaled system error (sse) bit is set high when ever the pm3351 asserts the serr* output. the sse bit is cleared by the pci host. dpe: the data parity error (dpe) bit is set high when ever the pm3351 detects a parity error, even if parity error handling is disabled by clearing peen in the command register. the dpe bit is cleared by the pci host. register 0x08: revision identifier/class code bit type function default bits 31 to 24 r ccode[23:16] 0x02 bits 23 to 16 r ccode[15:8] 0x00 bits 15 to 8 r ccode[7:0] 0x00 bits 7 to 0 r revid[7:0] 0x01 revid[7:0]: the revision identifier (revid[7:0]) bits specify a device specific revision identifier and are chosen by pmc-sierra. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 155 ccode[23:0]: the class code (ccode[23:0]) bits are divided into three groupings: ccode[23:16] define the base class of the device, ccode[15:8] define the sub-class of the device and ccode[7:0] specify a register specific programming interface. note: base class code: 0x02 network controller sub-class code: 0x00 ethernet network controller register class code: 0x00 none defined. register 0x0c: cache line size/latency timer/header type bit type function default bits 31 to 24 r bist[7:0] 0x00 bits 23 to 16 r hdtype[7:0] 0x00 bits 15 to 8 r/w lt[7:0] 0x00 or 0x20 bits 7 to 0 r/w clsize[7:0] 0x00 clsize[7:0]: the cache line size (clsize[7:0]) bits specify the size of the system cacheline in units of dwords. the pm3351 is not capable of generating the memory write and invalidate command so this register is hardwired to zeros. lt[7:0]: the latency timer (lt[7:0]) bits specify, in units of the pci clock, the value of the latency timer for the pm3351. the value of the lt is application specific and should be set appropriately by the pci bios at system initialization. the default value depends on the pcirun bit value set by the state on the mdata[31] pin when rst* is deasserted. if the pcirun bit defaults to a logic 0, the reset the value of lt[7:0] is zero. if the pcirun bit defaults to a logic 1, the reset the value of lt[7:0] is decimal 32. hdtype[6:0]: the header type (hdtype[7:0]) bits specify the layout of the first 64 bytes of the configuration space. only the 0x00 encoding is supported. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 156 bist[7:0]: built in self test (bist) is not implemented so the register is hardwired to zero. register 0x10 : local memory base address register bit type function default bits 31 to 24 r/w membase[27:20] mdata[25:22] or 0x00 bits 23 to 4 r fixbase[19:0] 0x00000 bit 3 r pf 0 bit 2 r type[1] 0 bit 1 r type[0] 0 bit 0 r msi 0 the pm3351 supports memory mapping only. at boot-up the internal registers space is mapped to memory space. the device driver can disable memory space through the pci configuration command register. msi: the memory space indicator (msi) bit is hardwired to zero to indicate that the pm3351 resources map into memory space. type[1:0]: the type field indicates where the internal registers can be mapped. the type field is set to 00b to indicate that the internal registers can be mapped anywhere in the 32 bit address space. pf: the prefetchable (pf) bit is set if there are no side effects on reads and data is returned on all the lanes regardless of the byte enables. otherwise the bit is cleared. the pf bit is hardwired to one to indicate that it is safe to prefetch data from the pm3351 register/memory resources. fixbase[19:0]: the fixed base address (fixbase[19:0]) bits define the size of the memory space required for the pm3351 resources. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 157 this 20-bit subfield is hardcoded to zero indicating the pm3351 register/memory resources can only be mapped into the pci address space on 16-megabyte boundaries. membase[27:20]: the memory base address (membase[27:20]) bits define location of the memory space required for the pm3351 resources. the membase[27:20] bits correspond to the most significant 8 bits of the pci address space. after determining the memory requirements of the pm3351 resources, the pci host can map them to its desired location by modifying the membase[27:20] bits. the default value depends on the pcirun bit value set by the state on the mdata[31] pin when rst* is deasserted. if the pcirun bit defaults to a logic 0, the reset the value of membase[27:20] is zero. if the pcirun bit defaults to a logic 1, the reset the value of membase[27:20] becomes the zero extended value of mdata[25:22] (which represents chipid[3:0). register 0x30: expansion rom base address bit type function default bits 31 to 0 r xrombase[31:0] 0x00000000 xrombase[31:0]: the pm3351 does not contain an expansion rom; therefore, this register is hardwired to zeros. register 0x3c: interrupt line / interrupt pin / min_gnt / max_lat bit type function default bits 31 to 24 r max_lat[7:0] 0x00 bits 23 to 16 r min_gnt[7:0] 0x03 bits 15 to 8 r intpin[7:0] 0x01 bits 7 to 0 r/w intline[7:0] 0x00 intlne[7:0]: the interrupt line (intlne[7:0]) field is used to indicate interrupt line routing information. the values in this register are system specific and set by the pci host. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 158 intpin[7:0]: the interrupt pin (intpin[7:0]) field is used to specify the interrupt pin the pm3351 uses. because the pm3351 will use inta* on the pci bus, the value in this register is set to one. min_gnt[7:0]: the minimum grant (min_gnt[7:0]) field specifies how long of a burst period the bus master needs. the pm3351 has a minimum grant of 750 ns (25 cycles). this register always returns 0x03. max_lat[7:0]: the maximum latency (max_lat[7:0]) field specifies how often a bus master needs access to the pci bus. the pm3351 has no specific requirements in this regard; this register always returns zero. register 0x40: merror / mrd / max. burst length bit type function default bits 31 to 25 r reserved 0x00 bits 24 r/w testdiscardtimer 0 bits 23 to 16 r/w tdiscon 0x6e bits 15 to 10 r reserved 0x00 bit 9 r mrd 0 bit 8 r merror 0 bits 7 to 0 r/w maxburstlen[7:0] 0x10 maxburstlen[7:0]: this register should be initialized with the maximum single-transaction burst length in dwords to be used by the pci bus master. it defaults to 16 dwords. merror: a logic one in this bit position indicates that the pci bus master has encountered a fatal error. mrd: a logic one in this bit position indicates that the pci bus master is currently performing a read transaction. tdiscon: the slave timer disconnect register is used to limit trdy and stop assertion based on the value in this register. tdiscon[3:0] sets the disconnect pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 159 delay for the first data access, while tdiscon[7:4] defines the disconnect delay for subsequent data phases of the same burst. note that the actual number of cycles, as measured from the start of the data phase to the cycle in which the disconnect is returned by the pci bus slave interface, is two greater than the numeric values programmed into the tdiscon[3:0] and tdiscon[7:4] fields. this register is for factory configuration purposes only. the value defaults to 0x6e (disconnect after 16 cycles on the first access and 8 cycles thereafter), and must remain at that value for correct operation. testdiscardtimer: this register bit allows testing of the discard timer feature in the pci bus slave logic. it defaults to zero. if set to logic 1, it causes the discard timer in the slave to be initialized to 0x2ff0 rather than 0x0000. this bit is for factory test purposes only. it must remain at logic 0 for correct operation. register 0x44: current master read address this register is provided for diagnostic purposes. bit type function default bits 31 to 0 r currmasterreadaddr 0x00000000 currmasterreadaddr[31:0]: current read target address used by pci bus master. register 0x48: current master write address this register is provided for diagnostic purposes. bit type function default bits 31 to 0 r currmasterwritea ddr 0x00000000 currmasterwriteaddr[31:0]: current write target address used by pci bus master. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 160 pci memory space the following table summarizes the mapping of the device resources to the pci address space: mnemonic pci offset description 0x000000- 0xfeffff local memory space (four banks) hstat 0xff0000 host interface status register hctrl 0xff0004 host interface control register mreg_addr 0xff0040 memory interface register address mreg_data 0xff0044 memory interface register data instcsr 0xff0048 ram/rom instruction control register instdata 0xff004c ram/rom instruction data register dibctrl 0xff0080 breakpoint/debug control/status register dpc 0xff0084 risc program counter depc 0xff0088 risc exception program counter dvec 0xff008c vector force address dibaddr1 0xff0090 instruction breakpoint #1 address dibmask1 0xff0094 instruction breakpoint #1 mask dibaddr2 0xff0098 instruction breakpoint #2 address dibmask2 0xff009c instruction breakpoint #2 mask dbgctrl 0xff00a0 debug functional block control register 0xff00a4- 0xfffeff unused, reserved rcount0 0xffff00 channel 0 request counter register rcount1 0xffff04 channel 1 request counter register rcount2 0xffff08 channel 2 request counter register rcount3 0xffff0c channel 3 request counter register rcount4 0xffff10 channel 4 request counter register rcount5 0xffff14 channel 5 request counter register rcount6 0xffff18 channel 6 request counter register rcount7 0xffff1c channel 7 request counter register acount0 0xffff20 channel 0 acknowledge counter register acount1 0xffff24 channel 1 acknowledge counter register acount2 0xffff28 channel 2 acknowledge counter register acount3 0xffff2c channel 3 acknowledge counter register acount4 0xffff30 channel 4 acknowledge counter register pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 161 acount5 0xffff34 channel 5 acknowledge counter register acount6 0xffff38 channel 6 acknowledge counter register acount7 0xffff3c channel 7 acknowledge counter register local memory access the external local memory is completely visible to the pci interface. direct memory access is provided to allow reads and writes to frame data, switching data structures, and configuration information. note that the uppermost 64 kbytes of the local memory space is not visible, as it is used for access to internal device registers. device control/status registers register 0x00ff0000: host interface status bit type function default bits 31 to 12 unused x bits 11 to 7 r hstate[4:0] 0 bit 6 r unused 0 bit 5 r rint 0 bit 4 r exti 0 bit 3 r rhalt 0 bit 2 r bkpt 0 bit 1 r merr 0 bit 0 r mperr 0 hstate: internal host interface state: for factory test purposes only rint: flags assertion of interrupt to host from switch processor exti: signals assertion of external interrupt input (mintr* pin) rhalt: switch processor halt status bkpt: switch processor breakpoint status merr: pci bus master catastrophic error status pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 162 mperr: pci bus master parity error detect register 0x00ff0004: host interface control bit type function default bits 31 to 16 unused x bit 15 r/w gres 0 bit 14 r/w mwbe 0 bit 13 r/w mrbe 0 bit 12 r/w swbe 0 bit 11 r/w srbe 0 bit 10 r/w h_epbe 0 bit 9 r/w ramdis 0 bit 8 r/w romdis 0 bit 7 r/w rhalt mdata[30] 1 bit 6 r/w reserved 0 bit 5 r/w rintmask 0 bit 4 r/w extmask 0 bit 3 r/w rhaltmask 0 bit 2 r/w bkptmsk 0 bit 1 r/w merrmsk 0 bit 0 r/w mperrmsk 0 gres: general device reset mwbe: pci master write byteswap enable mrbe: pci master read byteswap enable swbe: pci target (slave) write byteswap enable srbe: pci target (slave) read byteswap enable 1 the default value is the negation of the logical value on the specified pin when rst* is deasserted. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 163 h_epbe: ethernet payload byteswap enable mode bit, in host register space. the actual epbe mode bit setting is the logical or of h_epbe and cr_epbe (which is a similar mode bit in a control register accessible by the switch processor). ramdis: switch processor internal instruction ram disable romdis: switch processor internal instruction rom disable rhalt: switch processor halt enable control rintmsk: interrupt mask: enables interrupts from switch processor to host extmsk: interrupt mask: enables interrupts to host via mintr* input pin rhaltmsk: interrupt mask: enables interrupt to host when switch processor is halted bkptmsk: interrupt mask: enables interrupt to host when switch processor reaches pre- set breakpoint merrmsk: interrupt mask: enables interrupt to host on pci bus master catastrophic errors mperrmsk: interrupt mask: enables interrupt to host on pci bus master parity errors device configuration registers register 0x00ff0040: memory register bank address (mreg_addr) register 0x00ff0044: memory register bank data (mreg_data) the on-chip memory interface contains several registers that are accessible over the pci bus via the two registers mreg_addr and mreg_data. the user writes the applicable register select value to the mreg_addr register and then performs a read pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 164 (or write) to the mreg_data register to perform a pci bus read (or write) operation to the target register. the following table gives the indices for the registers in the on-chip memory interface. mreg_addr[3:0] register accessed description 0x0 mconfig memory configuration register 0x1 dconfig device configuration register 0x2 smr sdram mode register (reserved) 0x3 reserved 0x4 reserved 0x5 memctrl memory control/status 0x6 mstart_l memory statistics collection start 0x7 mstart_h 0x8 mstop_l memory statistics collection stop 0x9 mstop_h 0xa mccnt_l memory cycle count 0xb mccnt_h 0xc mwcnt_l memory write count 0xd mwcnt_h 0xe mrcnt_l memory read count 0xf mrcnt_h mreg_addr[31:4] bits are unimplemented so must be written with zero and ignored on reads. locations 0x5 through 0xf are for diagnostic purposes only. by way of example, the following the sequence of operations are required to first read the dconfig register and then write the mconfig register in the memory interface: pci write mreg_addr to 0x1 expansion address for dconfig pci read mreg_data read dconfig register pci write mreg_addr to 0x0 expansion address for mconfig pci write mreg_data to val[15:0] mconfig register written as val[15:0] note that the smr, memctrl, mstart, mstop, mwcnt and mrcnt registers are all reserved for factory testing, and must not be accessed during normal operation. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 165 mconfig (memory configuration register) bit type function default bits 31 to 16 unused x bits 15 to 14 r/w mxsel[1:0] mdata[15:14] 1,2 bit 13 r/w mslo mdata[13] 1,2 bit 12 r/w mdcas mdata[12] 1,2 bit 11 to 9 r/w mtype3[2:0] mdata[11:9] 1 bit 8 to 6 r/w mtype2[2:0] mdata[8:6] 1 bit 5 to 3 r/w mtype1[2:0] mdata[5:3] 1 bit 2 to 0 r/w mtype0[2:0] mdata[2:0] 1 mxsel[1:0]: these bits configure the dram row/column multiplexing to accommodate different dram organizations: mxsel column address bits 00 8 01 9 10 10 11 11 mslo: determines the expected access time of the local memory: if a logic 1, 80ns dram is expected; otherwise, 60ns dram is expected. if edo dram is used with the pm3351 for non-switching apllications it must be used with 60ns edo dram; hence, mslo must be a logic 0 for correct operation. mdcas: used to indicate the organization of dram used in the system, if any: if set to a logic 1, the elan 1x100 will generate control signals for 2-cas drams; otherwise, the elan 1x100 will assume 1-cas dram devices mtype3[2:0]: indicates the type of memory device selected with mcs[3]*: 000 reserved 001 reserved 010 15ns sram 011 reserved pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 166 100 reserved 101 150ns (e)eprom 110 60 ns edo dram 111 reserved mtype2[2:0]: indicates the memory type associated with mcs[2]*. the encoding is the same as mtype3[2:0]. mtype1[2:0]: indicates the memory type associated with mcs[1]*. the encoding is the same as mtype3[2:0]. mtype0[2:0]: indicates the memory type associated with mcs[0]*. the encoding is the same as mtype3[2:0]. note 1: the default value is the logical value on the specified pin when rst* is deasserted. note 2: while these bits are implemented on the elan 1x100 device they are not intended to be used for normal switching. dram memory types are supported for management and special applications purposes only. dconfig (device configuration register) bit type function default bits 31 to 16 unused x bit 15 r/w pcirun mdata[31] 1 bit 14 r/w riscrun mdata[30] 1 bit 13 r/w rsttm mdata[29] 1 bit 12 r/w imdis mdata[28] 1 bit 11 r/w pci3v mdata[27] 1 bit 10 r/w firm mdata[26] 1 bits 9 to 6 r/w chipid[3:0] mdata[25:22] 1 bits 5 to 0 r/w rtcdiv[5:0] mdata[21:16] 1 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 167 pcirun: this bit selects the operating mode of the pci interface. if logic 1: the on-chip pci interface will latch its slave base address from the chipid bits of the dconfig register. the pci command register bits for "bus master" and "memory space" are set to logic 1, thereby allowing the dvice to respond to pci memory space accesses and to be a bus master. if logic 0: the on-chip pci interface will has a slave base address of 0x0. the pci command register bits for "bus master" and "memory space" are set to logic 0; the device is disabled from responding to pci memory space accesses and will not be a bus master. riscrun: if set to zero, the switch processor enters a halt state immediately after system reset is deasserted, placing the elan 1x100 into stand-by mode. rsttm: for factory test purposes only: set to logic 0 for correct operation imdis: internal switch processor rom disable: if set to logic 1, the elan 1x100 switch processor begins execution from external memory after reset, otherwise it executes from internal rom. pci3v: if logic 1, configures the pci interface for the 3.3v signaling environment; otherwise, configures the pci interface for the 5v signaling environment. must be set to logic 0 since all ac parametric test data taken solely with this bit set to 0. firm: reserved for use by firmware; should be set to zero. chipid[3:0]: elan 1x100 chip identifier: these bits are zero-extended to 8 bits and loaded into the most significant byte of the pci memory base address register upon reset if the run bit is set. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 168 rtcdiv[5:0]: prescaler divide ratio for internal real-time clock. because the logical implementation of the divider the value of rtcdiv[5:0] is set to must be set to the numeric value of the sysclk frequency in megahertz less 1. that is, rtcdiv[5:0] = (f sysclk C1); e.g., 49 decimal when using a 50 mhz system clock). note 1: the default value loaded into the field is the logical value driven on to the specified pin when rst* is deasserted. register 0x00ff0048: ram/rom instruction control this register is reserved for factory test purposes, and should not be modified during normal operation. register 0x00ff004c: ram/rom instruction data this register is reserved for factory test purposes, and should not be modified during normal operation. device debug registers registers 0x00ff0080 - 0x00ff009c: debug control these registers are used to perform debug of switch processor operating code via the pci bus interface. they are reserved for factory test purposes, and should not be modified during normal operation. debug control/status register (dibctrl): pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 169 bit type function default bit 31 r/w vector force recognized 0 bits 30 to 9 unused, reserved 0 bit 8 r/w vector force enable 0 bit 7 r/w instruction cache flush 0 bit 6 r/w data cache flush 0 bit 5 r/w risc execption disable 0 bits 4 to 3 unused, reserved 0 bit 2 r/w risc breakpoint halt enable 0 bit 1 r/w breakpoint #2 enable 0 bit 0 r/w breakpoint #1 enable 0 registers 0x00ff00a0: debug functional block control register refer to the dbgctrl register for a description of this register. request and acknowledge counter registers registers 0x00ffff00 - 0x00ffff1c: request counters these counters are used for requests from a source device to a destination device across the pci bus. a write (of any arbitrary data) to one of these 32-bit locations increments the corresponding request counter by one. registers 0x00ffff20 - 0x00ffff3c: acknowledge counters these counters are used for acknowledges from a destination device to a source device across the pci bus. a write (of any arbitrary data) to one of these 32-bit locations increments the corresponding acknowledge counter by one. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 170 programmer's model this section outlines the interface between the pm3351 switch processor and the various internal functional blocks. this interface consists of the following: the control registers that are accessible by the switch processor the interrupts to the switch processor the mapping of the general purpose input lines (gpi) from the internal functional blocks to the switch processor the mapping of the general purpose output lines (gpo) from the switch processor to the internal functional blocks the mapping of the coprocessor test condition bits from the internal functional blocks to the switch processor normative reference on functional block names with respect to their description elsewhere in this document: dpi this refers to the dma transmit channel . this functional block is used to read a frame across the pci expansion bus and write it to the tx_fifo for transmit. dma unless otherwise noted, the dma functional block refers to the dma receive channel. dpo this refers to the dma transfer handshake channel. this is the name of the functional block that supports the eight transfer rings and the request and acknowledge counter increments to remote devices over the pci expansion bus. rpcim this refers to the pci access channel which allows the switch processor to initiate pci bus master transactions. pci_biu pci bus interface unit. the functional block that implements a pci revision 2.1 compatible pci bus master, bus slave (target), and configuration registers. tx_fifo transmit fifo. this functional block queues up ethernet frames that have pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 171 been read by the dma transmit channel before transmitting on the link media. local memory the elan 1x100 creates and uses data structures stored in an external local memory that is organized as a contiguous 16mb address space. memory addresses are 24 bits in width, and reference 8-bit bytes in little-endian form, i.e. the least-significant byte is located at the lowest byte offset within a 32-bit word, 24-bit tri-byte, or 16-bit halfword. register map general-purpose registers there are two banks of sixteen 16-bit general registers, gr0 through gr15 . they are used for all arithmetic operations, the source/destination of memory load/store operations, and for branch condition testing. access to these general registers is via cpu instructions. all general registers are identical; they are all readable and writeable by software. in general, one bank of 16-general registers is used for mainline code and the second bank of 16-general register is used during exception (i.e. interrupt routine) processing. the register bank is switched automatically when either taking or returning from an interrupt. switching of the register banks can also be done under explicit control of firmware by executing regsw instruction. the alternate registers are accessed with the same indices as the normal register set. special-purpose registers there are a total of 32 special-purpose registers that are used by the switch processor that are used solely by the processor for implementing the core processor instruction set: these include memory pointers, subroutine return addresses, exception control and status information, support ofthe microcode instructions, and implementation of the the real-time clock and alarms. the set of special purpose registers implemented by the elan 1x100 (pm3351) is the same as that implemented by the elan 8x10 device (pm3350). the contents of any special-purpose register may be accessed or modified by the move and ldi instructions. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 172 the memory pointers (mp0-mp6) are replaced by an alternate bank of registers when the regsw instruction is executed or an exception is taken. the alternate registers are accessed in the same way and by the same instructions as the main register set. mnemonic address register mp0l 0x00 memory pointer #0 (low) mp0h 0x01 memory pointer #0 (high) mp1l 0x02 memory pointer #1 (low) mp1h 0x03 memory pointer #1 (high) mp2l 0x04 memory pointer #2 (low) mp2h 0x05 memory pointer #2 (high) mp3l 0x06 memory pointer #3 (low) mp3h 0x07 memory pointer #3 (high) mp4l 0x08 memory pointer #4 (low) mp4h 0x09 memory pointer #4 (high) mp5l 0x0a memory pointer #5 (low) mp5h 0x0b memory pointer #5 (high) mp6l 0x0c memory pointer #6 (low) mp6h 0x0d memory pointer #6 (high) lnrl 0x0e link register (low) lnrh 0x0f link register (high) escl 0x10 exception status/control register (low) esch 0x11 exception status/control register (high) epcl 0x12 exception program counter (low) epch 0x13 exception program counter (high) emask 0x14 exception mask register offset 0x15 data segment offset register outcbl 0x16 microcode output control bits register (low) outcbh 0x17 microcode output control bits register (high) clockl 0x18 real-time clock counter register (low) clockh 0x19 real-time clock counter register (high) alarm1l 0x1a clock alarm #1 (low) alarm1h 0x1b clock alarm #1 (high) alarm2l 0x1c clock alarm #2 (low) alarm2h 0x1d clock alarm #2 (high) pcr 0x1e processor control register incb 0x1f microcode input control bits register pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 173 control registers there are a total of 96 16-bit control registers, cr0 through cr95 , that provide control and status of the functional blocks that comprise the pm3351. this set of control is, in general, device specific. for examplemost of the control register set of the elan 1x100 (pm3351) is different than that of the elan 8x10 device (pm3350). the control registers can be read by the risc only by using move instructions to transfer their contents to the general-purpose registers. the contents of any control register may be accessed or modified by the move and ldi instructions. some of the control registers may exhibit side effects when written to; these are noted in the register descriptions. registers that are marked as reserved are not to be written to. reads from reserved registers have no side-effects. in the table below the address column refers to the explicit address that is used by the switch processor for accessing the register via move and ldi instructions; the cr column refers to the control register number that is used for accessing the register when writing assembly code. for example, the dmstat register address is 0x21 but to move the contents of the register to the general register (say gr5), the assembly code is: "move cr1, gr5" mnemonic cr address register dmctrl cr0 0x20 dma control word dmstat cr1 0x21 dma status register instcsr cr2 0x22 ram/rom instruction control register instdata cr3 0x23 ram/rom instruction data register dmflistl cr4 0x24 dma free packetbuffer list pointer low (address bits [15:0]) dmflisth cr5 0x25 dma free packetbuffer list pointer high (address bits [23:16]) mreg_addr cr6 0x26 memory interface register address register mreg_data cr7 0x27 memory interface register data register smr cr8 0x28 reserved reqid cr9 0x29 request info ackid cr10 0x2a acknowledge info taskctr cr11 0x2b task counter dmnfreel cr12 0x2c dma next free packetbuffer low dmnfreeh cr13 0x2d dma next free packetbuffer high ctrsel cr14 0x2e request/ack counter select reg ctrdata cr15 0x2f request/ack counter data reg rpcicmd cr16 0x30 rpcim command register pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 174 rpcidata cr17 0x31 rpcim data register rpciaddrl cr18 0x32 rpcim address register high rpciaddrh cr19 0x33 rpcim address register low rpcistat cr20 0x34 rpcim status register wtimer cr21 0x35 rst module: watchdog timer frst cr22 0x36 rst module: firmware rst register dbgctrl cr23 0x37 dbg module control register dpi_dd0l cr24 0x38 dpi: data descriptor word 0, low halfword (bits [15:0]) dpi_dd0h cr25 0x39 dpi: data descriptor word 0, high halfword (bits [31:16]) dpi_dd1l cr26 0x3a dpi: data descriptor word 1, low halfword (bits [15:0]) dpi_dd1h cr27 0x3b dpi: data descriptor word 1, high halfword (bits [31:16]) dpi_dd2l cr28 0x3c dpi: data descriptor word 2, low halfword (bits [15:0]) dpi_dd2h cr29 0x3d dpi: data descriptor word 2, high halfword (bits [31:16]) dpi_dd3l cr30 0x3e dpi: data descriptor word 3, low halfword (bits [15:0]) dpi_dd3h cr31 0x3f dpi: data descriptor word 3, high halfword (bits [31:16]) dpi_ctrl cr32 0x40 dpi: control/status register txf_wsize cr33 0x41 tx fifo: write size register (at fifo tail) dpi_rddl cr34 0x42 dpi: remote dd address, low halfword (bits [15:0]) dpi_rddh cr35 0x43 dpi: remote dd address, high halfword (bits [31:16]) txf_csr cr36 0x44 tx fifo control/status reg txf_raddr cr37 0x45 tx fifo read address pointer (within fifo) txf_waddr cr38 0x46 tx fifo write address pointer (within fifo) txf_dsize cr39 0x47 tx fifo: size of frame transmitted on mac transmit link media txf_datal cr40 0x48 tx fifo: switch processor read/write data reg, low halfword txf_datah cr41 0x49 tx fifo: switch processor read/write data reg, high halfword txf_valid cr42 0x4a tx fifo: write/read byte enables pbsize cr43 0x4b packet buffer size register. used for packetbuffers in devices local memory rpbsize cr44 0x4c remote packet buffer size register. used for reading packetbuffers over pci expansion bus. ipcidatal cr45 0x4d dpo: pci increment counter write data, low halfword ipcidatah cr46 0x4e dpo: pci increment counter write data, high halfword ichip_mask cr47 0x4f dpo: transfer handshake channel chip mask idd0l cr48 0x50 dpo: transfer handshake channel data descriptor word 0, bits [15:0] idd0h cr49 0x51 dpo: transfer handshake channel data descriptor word 0, bits [23:16] idd1l cr50 0x52 dpo: transfer handshake channel data descriptor word 1, pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 175 bits [15:0] idd1h cr51 0x53 dpo: transfer handshake channel data descriptor word 1, bits [23:16] idd2l cr52 0x54 dpo: transfer handshake channel data descriptor word 2, bits [15:0] idd2h cr53 0x55 dpo: transfer handshake channel data descriptor word 2, bits [23:16] idd3l cr54 0x56 dpo: transfer handshake channel data descriptor word 3, bits [15:0] idd3h cr55 0x57 dpo: transfer handshake channel data descriptor word 3, bits [23:16] idd0flag cr56 0x58 dpo: transfer handshake channel data descriptor word 0, bits [31:24] idd1flag cr57 0x59 dpo: transfer handshake channel data descriptor word 1, bits [31:24] idd2flag cr58 0x5a dpo: transfer handshake channel data descriptor word 2, bits [31:24] idd3flag cr59 0x5b dpo: transfer handshake channel data descriptor word 3, bits [31:24] ic_ctrl cr60 0x5c dpo: transfer handshake channel control/status register ic_data cr61 0x5d dpo: transfer handshake channel ring data access register dstail cr62 0x5e tx fifo logic: disposition fifo, tail register (write interface) dshead cr63 0x5f tx fifo logic: disposition fifo, head register (read interface) lc_sel cr64 0x60 link: link constant register address lc_data cr65 0x61 link: link constant register data hashctrl cr66 0x62 hash logic: control/status register hmask cr67 0x63 hash array size mask hbasel cr68 0x64 hash array base low (address bits [15:0]) hbaseh cr69 0x65 hash array base high (address bits [23:16]) hdpisrcrl cr70 0x66 hash result register: dpi source address, low (address bits [15:0]) hdpisrcrh cr71 0x67 hash result register: dpi source address, high(address bits [23:16]) hdmadstrl cr72 0x68 hash result register: link rx frame destination address, low (address bits [15:0]) hdmadstrh cr73 0x69 hash result register: link rx frame destination address, high (address bits [23:16]) hdmasrcrl cr74 0x6a hash result register: link rx frame source address, low (address bits [15:0]) hdmasrcrh cr75 0x6b hash result register: link rx source address, high (address bits [23:16]) pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 176 hdpisrcl cr76 0x6c hash dpi source mac address, low 16-bits hdpisrcm cr77 0x6d hash dpi source mac address, mid16-bits hdpisrch cr78 0x6e hash dpi source mac address, high 16-bits hdmadstl cr79 0x6f hash link rx destination mac address, low 16-bits hdmadstm cr80 0x70 hash link rx destination mac address, mid 16-bits hdmadsth cr81 0x71 hash link rx destination mac address, high 16-bits hdmasrcl cr82 0x72 hash link rx source mac address, low 16-bits hdmasrcm cr83 0x73 hash link rx source mac address, mid 16-bits hdmasrch cr84 0x74 hash link rx source mac address, high 16-bits lwctrl cr85 0x75 link control register lwstat cr86 0x76 link status register lwback cr87 0x77 link transmit backoff timer lwnbufs cr88 0x78 link receive: number of packetbuffers in received frame lwfirstl cr89 0x79 link receive: address of first packetbuffer in received frame (address bits [15:0]) lwfirsth cr90 0x7a link receive: address of first packetbuffer in received frame (address bits [23:16]) lwlastl cr91 0x7b link receive: address of last packetbuffer in received frame (address bits [15:0]) lwlasth cr92 0x7c link receive: address of last packetbuffer in received frame (address bits [23:16]) lwdsize cr93 0x7d link receive frame size (in bytes) ackrptr cr94 0x7e dpo: acknowledge pointer for transfer ring valid during acknowledge interrupt txf_rsize cr95 0x7f tx fifo: read size register (at head of fifo) register descriptions cpu special registers register 0x00-0x0d: memory pointers #0 - #6 register 0x0e, 0x0f: link register register 0x10, 0x11: exception status register register 0x12, 0x13: exception program counter pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 177 register 0x14: exception mask register register 0x15: data segment offset register register 0x16, 0x17: microcode output control bits register register 0x18, 0x19: real-time clock counter register register 0x1a, 0x1b: clock alarm #1 register 0x1c, 0x1d: clock alarm #2 register 0x1e: processor control register register 0x1f: microcode input control bits register device control registers register 0x20 (cr0): dma control register (dmctrl) bit type function default 15 r/w reserved 0 14:13 r/w cop_reg [15:14] 0 12:9 r/w unused 0 8 r/w select_dmstat2 0 7:4 r dma state compare 0 3 r/w cr_epbe 0 2 r/w lbk pin low true 0 1 r/w lbk mode 0 0 r/w halt dma 1 cop_reg[15:14]: software settable register bits that map to the switch processor coprocessor test condition bits [15:14]. select_dmsat2: select for dmstat register. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 178 (0) C dmstat1 register is read via dmstat control register. (1) C dmstat2 register is read via dmstat control register. dma state compare: this register field is compared to the value of the dma state machine. the comparison is output on the dma_state_hit signal (0 is not equal; 1 is equal), which is observable via the debug logic interface. cr_epbe: ethernet packet big endian mode bit, control register space. the epbe setting for the pm3351 is simply the logical or of the epbe mode bit that is in the hctrl register (in pci register space, h_epbe) and this bit (in switch processor control register space). lbk pin low true: the logical state of the lbk pin on the pm3351 is the xor of this bit with the lbk mode bit. this allows the lbk pin of the device to interface directly to ethernet phy devices that use a low-true or high-true version of lbk. lbk mode: when set, the link interface on the pm3351 is configured for loopback. this configuration affects both the logical value of the lbk pin of the device and the operation of the link interface. when the lbk mode bit is set the link will continuously transmit a single byte (see loopback byte link constant register) on the mii interface. the link receiver is unaffected by this mode bit. if the data on the mii receive interface is consistent with a valid receive frame (correct preamble and startofframe delimiter) then the frame data will be received and formatted into packetbuffers as is the case for normal frame reception. register 0x21 (cr1) dma status register (dmstat) this register is used to read one of two dma status registers depending on the setting of the dmctrl.select_dmstat2 register bit. both dmstat1 and dmstat2 are implemented solely for device debug and are not required to be accessed by firmware during normal operation of the device. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 179 dmstat1 register bit definition: bit type function default 15 r free packetbuffer list lock state (switch processor sets this bit before accessing the dmflist register; this is typically done when the firmware is reallocating packetbuffers during the acknowledge interrrupt service routine. the dma hardware is locked out of accessing free packetbuffer pool when this bit is set). 0 14 r free list error interrupt state 0 13 r ethernet packet big endian mode setting (logical or of hctrl.h_epbe and dmctrl.cr_epbe). 0 12 r unimplemented 0 11 r last_done state bit (set when last rxframe byte is read from the link receive fifo; cleared in dma state frame_done). 0 10 r ln_first state bit (state bit that is set in-between receive frames. this bit is continuously set when the dma state is idle. it is cleared as soon as the first data byte of a received frame is read from the link receive fifo). 1 9:6 r dma state 0 5 r rx_ctrl_frame 0 4 r rx_fifo_ovrun 0 3 r rxlong 0 2r rxshort 0 1 r rx_crc_err 0 0 r rx_misalign 0 rx_ctrl_frame: receive frame status: a frame was received having an ethernet length/type field of the same value as the etype link control register. status valid when a receive frame interrupt is asserted. rx_fifo_ovrun: receive frame status: a fifo over-run occurred in the link receiver during reception of this frame. status valid when a receive frame interrupt is asserted. rxlong: receive frame status: a frame was received with a length greater than that of pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 180 the max_size link control register value. status valid when a receive frame interrupt is asserted. rxshort: receive frame status: a frame was received with a length less than that of the min_size link control register value. status valid when a receive frame interrupt is asserted. rx_crc_err: receive frame status: a frame was received having an incorrect 802.3 framechecksequence field (that is, a crc error). status valid when a receive frame interrupt is asserted. rx_misalign: receive frame status: this bit is set (1) if an odd number of framed data nibbles were received on the mii receive interface. the bit is clear (0) if an even number of framed data nibbles were received. status valid when a receive frame interrupt is asserted. dmstat2 register bit definition: bit type function default 15:12 r unimplemented 0 11 r start_xfr state bit (dma sets this bit to initiate a burst access to the local memory interface. valid in dma state wait_xfr). 0 10 r link receive fifo read enable status 0 9 r pbxfrdone state bit (dma state bit that is set when all data has been written into the present packetbuffer: either packetbuffer is full or the last byte of the rx frame is in it.) 0 8 r endofframe status (dma determines from link receive fifo interface signals) 0 7:0 r ln_size[7:0] (number of valid data bytes in packetbuffer presently allocated to the dma). 0 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 181 register 0x23 (cr2): ram/rom instruction control register (instcsr) bit type function default bit 15 r/w rampr 0 bit 14 r/w rompr 0 bit 13 unused 0 bit 12 r/w rw 0 bit 11 r/w hl 0 bit 10 to 0 r/w addr[10:0] 0 rampr: program (1) or execute (0) contents of ram rompr: program (1) or execute (0) contents of rom rw: select between write (1) and read (0) of the instdata register hl: select high (1) bank or low (0) bank of instdata for control data. addr[10:0]: ram/rom instruction address. only low 7 bits of the address are used for rom accesses. register 0x23 (cr3): ram/rom instruction data register (instdata) bit type function default bit 15 to 0 r/w idata[15:0] 0 idata[15:0]: the register operates in conjunction with the ram/rom instruction control register (cr2) to read and write the internal instruction ram and rom. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 182 register 0x24 (cr4): dma freelist pointer low (dmflistl) bit type function default bit 15 to 0 r/w flist[15:0] 0 register 0x25 (cr5): dma freelist pointer high (dmflisth) bit type function default bit 15 to 8 unused x bit 7 to 0 r/w flist[23:16] 0 flist[23:0]: the freelist pointer locates the head of the linked list of free packet buffers within the local memory. these registers are modified by either the switch processor or by the dma logic. during normal switching applications they are used as follows: the dma deallocates packetbuffers from the freelist during reception of frames on the mii interface. it does this on a packetbuffer Cby-packetbuffer basis by following the nextptr field of the packetbuffer that is pointed to by the current dmflist entry. the dma keeps the pointer for the next packetbuffer it will be using in the dmnfree[23:0] control register. the switch processor reallocates the entire linked-list of packetbuffers in a frame after the frame has been acknowledged to have been read across the pci expansion bus by the required number of elan devices (which is when the refcount field of the packetbuffer has decremented to 0 - refer to the elan switch protocol discussion for additional information). packetbuffers are reallocated on the head of the freelist. hence, the dmflist will be updated with a pointer to the first packetbuffer in the frame that is being reallocated to the freelist. there is a simple hardware interlock that is provided to allow the dma and the switch processor to read and write the dmflist register. the switch processor does this by means of two flip instructions that set and clear a freelist lock signal (flist_lock). the switch processor has priority for accessing the freelist. if the freelist lock is set while the dma is currently accessing the freelist, the dma will abort the present access and will attempt to access the freelist only after the freelist lock is deasserted by the switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 183 register 0x26 (cr6): memory register bank address (mreg_addr) register 0x27 (cr7): memory register bank data (mreg_data) the on-chip memory interface contains several registers that are accessible over the pci bus via the two registers mreg_addr and mreg_data. the user writes the applicable register select value to the mreg_addr register and then performs a read (or write) to the mreg_data register to perform a pci bus read (or write) operation to the target register. these registers are accessible by the pci expansion bus. refer to the pci accessible registers section for details on the use of these registers. register 0x29 (cr9): request info (reqid) bit type function default bit 15 r reqid_valid 0 bit 14 r req_int 0 bit 13 to 7 unused 0 bit 6 to 4 r reqid_num[2:0] 0x7 bit 3 to 0 unused 0 reqid_valid: valid bit - there is a request pending. qualifies reqid_num. req_int: request interrupt status (for observability; not used by firmware during normal switching). reqid_num[2:0]: requesting chip number. this is used by the switch processor firmware during service of a request interrupt. this number is selected by dedicated hardware (counter bank support logic) on the pm3351 that examines all eight of the request counters (these are rcount0 through rcount7). it takes a snapshot of which of these counters is non-zero (request snapshot register) and services them in order from rcount0 to rcount7. the switch processor signals to the logic that the current reqid_num has been completed by doing a flip (req_dec). this clears the bit in the request snapshot register for the currently selected counter, which allows the reqid_num to be updated with the next request counter number (which is only valid if the reqid_valid bit is also set). a pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 184 new snapshot of the request counters is taken whenever the following two conditions are met: (1) the request snapshot register is zero. (2) at least one of the rcount0 through rcount7 registers is non-zero. register 0x2a (cr10): acknowledge info (ackid) bit type function default bit 15 r ackid_valid 0 bit 14 r ack_int 0 bit 13 to 7 unused 0 bit 6 to 4 r ackid_num[2:0] 0x7 bit 3 to 0 unused 0 this is used by the switch processor firmware during service of an acknowledge interrupt. implementation of ackid_num is similar to reqid_num with the following differences: there is an acknowledge snapshot register the switch processor does an ack_dec flip to signal completion of the service routine for the selected ackid_num. register 0x2b (cr11): task counter (taskctr) bit type function default bit 15 to 0 r/w tcount[15:0] 0 tcount[15:0]: this register implements a 16-bit up-down counter. the counter is incremented and decremented under control of the switch processor: the counter is incremented if the task counter increment flip is asserted (task_inc). the counter is decremented if the task counter decrement flip is asserted (task_dec) Cand- task_inc is not simultaneously asserted. if the tcount[15:0] register is non-zero, the taskcounter interrupt is asserted to the switch processor. note: the present firmware implementation of the pm3351 does not use this counter. it may be used in future firmware releases. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 185 register 0x2c: dma next free packet buffer low (cr12) bit type function default bit 15 to 0 r/w nfree[15:0] 0 register 0x2d: dma next free packet buffer high (cr13) bit type function default bit 15 to 8 unused x bit 7 to 0 r/w nfree[23:16] 0 nfree[23:0]: the next free pointer is the address in local memory of the next available packet buffer. these registers are modified by either writes by the risc or by the dma upon transfer of the packet buffer. register 0x2e (cr14): request/ack counter select reg (ctrsel) bit type function default bit 15 r/w ctrseltm 0 bit 14 r/w en_wr_counter 0 bit 13 r/w disable_req_int 0 bit 12 r/w disable_ack_int 0 bit 11 to 4 unused 0 bit 3 to 0 r/w ctrsel[3:0] 0 during normal switching applications the ctrlsel register will be left in the default state and is unused. it is implemented solely for factory test. ctrseltm: the testmode bit for counter bank testing. this bit must be a logic 0. en_wr_counter: when set to a logic 1, this bit allows req/ack counters to be written by the switch processor. disable_req_int: when set to a logic 1, this bit disables the generation of the req_int interrupt line. disable_ack_int: when set to a logic 1, this bit disables the generation of the ack_int interrupt line. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 186 ctrsel[3:0]: selects the counter to view . ctrsel[3:0] ctrdata[11:0] 0000 rcountq0 0001 rcountq1 0010 rcountq2 0011 rcountq3 0100 rcountq4 0101 rcountq5 0110 rcountq6 0111 rcountq7 1000 acountq0 1001 acountq1 1010 acountq2 1011 acountq3 1100 acountq4 1101 acountq5 1110 acountq6 1111 acountq7 register 0x2f (cr15): request/ack counter data reg (ctrdata) bit type function default bit 15 to 0 r/w ctrdata[15:0] 0 during normal switching applications the ctrdata register will be left in the default state and is unused. it is implemented solely for factory test. ctrdata[15:0]: the data from the selected counter bank. this allows the switch processor to read or write one of the eight rcount or eight acount registers that are also mapped into the pci host register space. the switch processor can read a selected request or acknowledge counter as follows the ctrsel register is written with the ctrsel.en_wr_counter bit clear (0) and the ctrsel[3:0] field set to access the desired counter. there is a minimum of one processor delay slot pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 187 the value of the selected counter can be read from the ctrdata register using the move assembly instruction. the switch processor can write a selected request or acknowledge counter as follows: the ctrsel register is written with the ctrsel.en_wr_counter bit set (1) and the ctrsel[3:0] field set to access the desired counter. the switch processor uses the move or ldi assembly instructions to write the desired value to the ctrdata register. on the cycle after ctrdata is written by the switch processor the write data updates the selected request/acknowledge counter. rpcim functional block (pci access dma channel) the purpose of the rpcim logic block on the pm3351 is to allow the switch processor to directly initiate pci bus master transactions: memory read transactions memory write transactions configuration read transactions configuration write transactions in normal ethernet switching applications firmware will only utilize the rpcim logic during system initialization; it is the various dedicated dma channels on the pm3351 that are used to initiate all of the pci master transactions on the pci expansion bus that are required by the elan switch protocol. during system initialization all of the pci bus transactions that the master chip in a system does to initialize slave chips is done utilizing the rpcim logic block. outline of rpcim memory/configuration write transactions: for write transfers, the data to be written to the pci bus must be broken up into a sequence of transactions that are from 1 to 63 bytes in size. the data to be written to the pci bus is held in an internal rpcim data fifo which is accessible via writes to the rpcidata register. the data fifo write pointer is auto-incremented on each write to the rpcidata register. the transfer is initiated by writing to a series of switch processor accessible control registers: rpciaddr (address) and rpcicmd (command related). the write to the rpcicmd register signals the rpcim internal state machine to start the pci master write transaction. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 188 the rpcim must arbitrate with the other internal dma channels that can initiate pci write transactions for access to a shared hardware resource: the pci master write fifo (mwf fifo) that is part of the internal pci bus interace unit (pci_biu). the arbiter for access to the mwf fifo is internal to the rpcim logic. the grant for the write interface, `rwr_gt', is set on the cycle before the rpcim writes the command word in the mwf fifo. upon writing the last word of the command/address/data into the mwf fifo for a given transaction, the following occurs concurrently: the rpcim_done line is asserted (this maps to one of the interrupt lines on the pm3351 switch processor). rwr_gt is deasserted; this allows another dma channel to perform pci write transactions. on the pci bus the write transaction will appear as a single burst transaction of "bytecount" bits. the switch processor takes the rpcim_done interrupt: switch processor does a clr_rpcim_done flip at beginning of the interrupt routine, which deasserts the rpcim_done interrupt and clears state of the rpcim module (returns the internal state machine to idle and resets data fifo write and read pointers). if (the switch processor wants to continue the dma transfer) the switch processor firmware computes the next pci address and writes the new bytewriteaddress into rpciaddr: bytewriteaddress = bytewriteaddress + sizeof_last_bytecount (which is probably 64); switch processor firmware writes data for the next transfer to the rpcidata register switch processor writes the rpcimd register with bytecount of new transaction. outline of rpcim memory/configuration read transactions: although there is only one hardware mode of operation for performing read transactions the switch processor firmware can determine how transactions of larger than 64 bytes are handled: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 189 whether the entire block transfer will occur on the pci bus as a single pci bus transaction (which may result in greater latency of other internal pci master read consumers to complete a pci read transaction). the maximum number of bytes that can be read in a single transaction by the pm3351 is 255. or as a series of 1-64 bytes transactions. the pci read transaction will occur on the pci bus as one burst read transaction. the pci read transfer is initiated by writing the rpciaddr and rpcicmd registers. the write to the rpcicmd register signals the rpcim internal state machine to start the pci master read or configuration read transaction. the rpcim must arbitrate with the other internal dma channels that can initiate pci read transactions for access to a shared hardware resource: the master read command (mcf) and master read data (mrf) fifos that are part of the internal pci bus interface logic (pci_biu). the arbiter for access to the mcf/mrf fifos is internal to the rpcim logic. the grant for the read interface, `rrd_gt', is set on the cycle before the rpcim logic writes the mcf cmd word to the mcf fifo. when the desired read transaction is occuring on the pci bus the read data is written into the internal rpcim data fifo until the first of these occur: 64 bytes of data have been read from the mrf fifo or the internal bytecount size field has decremented to 0 indicating that all data has been read. the rpcim_done line is asserted indicating that the switch processor can burst read the rpcimdata register to access the read data. coincident with assertion of rpcim_done, if the next_bytecount field has decremented to `0' then the internal arbiter bit "rrd_gt" is deasserted (this will always be true if rpcim.bytecount is never written to greater than 64). next_bytecount is an internal counter that is preloaded with bytecount and decrements as data is read. the switch processor takes the rpcim_done interrupt: switch processor reads the read data from the rpcimdata control register. every read returns either one or two valid data bytes and increments the internal rpcim data register address and decrements next_bytecount. after the switch processor has read all of the data that it wants to read out of the rpcim data fifo it pulses the `clr_rpcim_done' line. upon assertion of the `clr_rpcim_done' line the rpcim_done line is deasserted and next_bytecount is assigned to rpcim.bytecount. if rpcim.bytecount is `0' pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 190 then the present transaction is done and the `rpcim_idle' output is asserted. however, if the rpcim.bytecount field is greater than `0' (which would have occured only if the initial bytecount was greater than 64) the master read fifo continues to be read and the data written to the rpcim data fifo. as previously stated, the internal `rrd_gt' signal is always deasserted when it has been determined that the last byte of the pci read transaction has been read by the rpcim module from the mrf fifo into the rpcim internal data fifo. rpcim data fifo: data alignment the rpcim module does no alignment of data with respect to data written to the mwf fifo and data read from the mrf fifo. the internal pci bus interface logic is expecting that data is left aligned with respect to these fifos: if a single byte of data is to be written on the pci bus, the mwf fifo is expecting the data to be on bytelane 3. if a single byte of data is to be read from the pci bus, the mrf fifo will return the data byte on bytelane 3. this data alignment is preserved in accessing the rpcim data fifo using the rpcidata register. data to be written to the mwf fifo is written into the rpcidata register from "left-to-right" and "first-to-last" order. this is regardless to the actual byte address offset (i.e. ad [1:0] of the transaction as it appears on the pci bus during the address phase of the transaction). so if a 5-byte write transaction is desired, with d0 representing the data to be written starting at the 32-bit bytewriteaddress and d4 the data to be written to "bytewriteaddress+4" the switch processor firmware must do the following: write rpcimaddrh/l register to "bytewriteaddress" write rpcidata with first two data bytes: {d0,d1} write rpcidata with next two data bytes: {d2,d3} write rpcidata with last data byte: {d4,8'h0} write the rpcicmd register: bytecount=8'h5, cmd[1:0]=memory_write_cmd data alignment on read transactions is similar. data to be read from the mrf fifo is read from the rpcidata register from "left-to-right" and "first-to-last" order. once again, this is regardless to the actual byte address offset as seen on the pci bus during the address phase of the read transaction. so if a 5-byte read transaction is desired, pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 191 with d0 representing the data read from bytereadaddress and d4 the data be read from "bytereadaddress+4" the switch processor firmware must do the following: write rpcimaddrh/l register to "bytereadaddress" write the rpcicmd register: bytecount=8'h5, cmd[1:0]=memory_read_cmd the read transaction will then occur on the pci bus. after the transaction has completed and all 5 data bytes are in the rpcim data fifo, the rpcim_done interrupt is asserted. during the firmware service routine the switch processor will read the rpcidata register: 1st read from rpcidata returns first two data bytes: {d0,d1} 2nd read from rpcidata returns next two data bytes: {d2,d3} 3rd read from rpcidata returns the last data byte: {d4,8'hx} rpcim: zero-length transactions if the switch processor firmware tries to initiate an rpcim transaction having a bytecount of size `0' then the rpcim internal state machine will not leave state idle. rpcim: writing to rpcicmd.bytecount field if the rpcim is not idle if the `rpcim_idle' coprocessor test condition line returns 0 (indicating that the rpcim module has a transaction in progress) then the bytecount field of the rpcicmd register must not be written. doing so will lead to unexpected and possibly fatal results (i.e. pci bus master error). rpcim: internal arbitration to pci_biu shared hardware resources since the rpcim must share the pci_biu master write and read hardware with other pci (i.e. dma) write and read channels on the pm3351 there must be some way to determine which consumer is getting access to the interface. this is accomplished using a simple request-grant protocol. on the pm3351 the request/grant protocol betweent the rpcim logic and the various other dma channels is done completely in hardware and is transparent to the programmer. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 192 register 0x30 (cr16): rpcim command register (rpcimcmd) bit type function default 15 unused 0 14 r merr 0 13 r/w merge 0 12 r/w bswp 0 11:10 unused 0 9:8 r/w cmd 0 7:0 r/w bytecount 0 merr: pci bus interface logic master error status. merge: this is the value of the `merge' bit in the command word written to the pci_biu mwf/mcf fifo. it must be written to a logic 0 for correct device operation (a pci bus transaction master abort will occur if the bit is incorrectly written to a logic 1). bswp: this is the value of the `byteswap' bit in the command word written to the mwf/mcf fifo. byte-swap swaps the way that bytes are presented on the pci bus (refer to description on byte ordering for additional details). cmd[1:0]: defines type of transfer to be performed. 00 - memory read command 01 - memory write command 10 - configuration read command 11 - configuration write commands bytecount[7:0]: byte count of pci transaction. when non-zero, a pci transaction will be initiated. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 193 register 0x31 (cr17): rpcim data register (rpcidata) bit type function default 15:0 r/w rpcidata[15:0] 0 rpcidata[15:0]: rpcim data fifo access register. for memory write or configuration write transactions, data that is to be written to the pci bus is first written to this register. for memory read or configuration read transactions, the data that was read during the pci transaction is available by reading this register. register 0x32 (cr18): rpcim address register low (rpcimaddrl) bit type function default 15:0 r/w rpciad[31:16] 0 register 0x33 (cr19): rpcim address register high (rpcimaddrh) bit type function default 15:0 r/w rpciad[15:0] 0 rpciad[31:0]: the contents of this register are used as the address for the pci transaction that is initiated by the rpcim logic. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 194 register 0x34 (cr20): rpcim status register (rpcistat) bit type function default bit 15 to 12 r s[3:0] 0 bit 11 to 8 unused 0 bit 7 r rwr_gt 0 bit 6 r dmapwr_gt 0 bit 5 r rwr_rq 0 bit 4 r dmapwr_rq 0 bit 3 r rrd_gt 0 bit 2 r dmaprd_gt 0 bit 1 r rrd_rq 0 bit 0 r dmaprd_rq 0 s[3:0]: current state of rpcim state machine rwr_gt: write grant to rpcim for access to internal pci_biu master write interface. dmapwr_gt: write grant to other dma channels for access to internal pci_biu master write interface. rwr_rq: rpcim request for access to internal pci_biu master write interface. dmapwr_rq: other dma channels request access to internal pci_biu master write interface. rrd_gt: read grant to rpcim for access to internal pci_biu master read interface. dmaprd_gt: read grant to other dma channels for access to internal pci_biu master read interface. rrd_rq: rpcim request for access to internal pci_biu master read interface. dmaprd_rq: dma request for access to internal pci_biu master read interface. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 195 register 0x35 (cr21): rst module: watchdog timer (wtimer) bit type function default bit 15 to 0 r/w wtimer[15:0] 0xffff the watchdog timer provides the ability for the device to generate a reset if program execution experiences a fatal delay. by default, this feature is disabled. the hardware associated with the watchdog reset is: a prescaler for the 50 mhz sysclk that divides it down to get a pulse every 1 millisecond a 16-bit counter driven from the 1 millisecond pulse a comparator that checks when the counter is either 0 or 0x ffff (decimal 65535) disable logic that stops the counter if it is 0xffff if firmware running on the switch processor want to maintain a watchdog timer then it simply loads the wtimer register with a non-zero value that is less than 0xffff; the wtimer register w ill count down in 1 msec intervals and ultimately cause a chip reset when it reaches zero unless the switch processor reloads the wtimer register with a new non-zero value. when the wtimer register decrements to 0x0000 (this event is called a watchdog timeout) the wtimer register will roll-over to 0x ffff after 1 m illisecond. in the event of a watchdog timeout, the following occurs: reset is applied for 1 millisecond internal to the core logic on the pm3351 device. this includes resetting all internal logic (including the switch processor itself) except for the pci bus interface logic. the erst_ output will be asserted for 10 milliseconds. as previously described, the erst_ output is open drain and can be tied directly to the rst_ input of all of the elan 1x100 and elan 8x10 chips in a system. if erst_ is directly connected to rst_, then a watchdog timeout occuring on any of these devices will cause a hardware reset to be applied for 10 milliseconds; this hardware reset will reset the core logic and the pci bus interface logic of each of the elan 1x100 and elan 8x10 devices. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 196 wtimer[15:0]: the binary value of the register is decremented every millisecond provided it is not 0xffff. when the count reaches 0x0000, the device will be reset for 1ms. if the risc wants to turn off the watchdog, it loads the counter with 0xffff. this is also the default state upon assertion of the rst* input. if the risc wants an immediate reset via software, it loads the counter with 0x0000. register 0x36 (cr22): rst module: firmware rst reg (frst) bit type function default bit 15 r/w f_erst 0 bit 14 r/w unused 0 bit 13 r/w mrst 0 bit 12 r/w dbg_rst 0 bit 11 to 8 r/w unused 0 bit 7 r/w dpo_rst 0 bit 6 r/w txf_rst 0 bit 5 r/w dpi_rst 0 bit 4 r/w link_rst 0 bit 3 r/w dma_rst 0 bit 2 r/w rpcim_rst 0 bit 1 r/w hash_rst 0 bit 0 r/w ctr_bank_rst 0 f_erst: if f_erst transitions from logic 0 to logic 1, the erst_ output pin is asserted (i.e. driven to ttl logic 0) for 10 ms (assuming 50mhz sysclk). mrst: if this bit is a logic 1, the internal pci bus interface logic associated with being a bus master is reset. dbg_rst: if this bit is a logic 1, the logic associated with the debug functional block is reset. dpo_rst: if this bit is a logic 1, the logic associated with the dpo (i.e. transfer handshake channel) functional block is reset. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 197 txf_rst: if this bit is a logic 1, the transmit fifo functional block is reset. dpi_rst: if this bit is a logic 1, the logic associated with the dpi functional block is reset (the dpi is the abbreviated name of the dma transmit channel). link_rst: if a link_rst bit is a logic 1, the link functional block is held in its reset state. dma_rst: if this bit is a logic 1, the dma functional block is held in its reset state. rpicm_rst: if this bit is a logic 1, the rpcim functional block is held in its reset state. hash_rst: if this bit is a logic 1, the hash functional block is held in its reset state. ctr_bank_rst: if this bit is a logic 1, the counter bank functional block is held in its reset state. debug functional block the debug functional block is provided to assist in factory debug of the device during system verification. it provides the facility for displaying certain internal device data on three pins of the pm3351. the hardware associated with the debug module includes: a snapshot register that can capture and display the switch processor program counter, 2-bits at a time. a 128:1 serial mux for displaying one of 128 possible internal signals pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 198 register 0x37: debug module control register (cr23) bit type function default bit 15 unused x bit 14 to 8 r/w ssel[6:0] 0 bit 7 to 4 unused x bit 3 r/w dbgmode[2] 0 bit 2 r/w dbgmode[1] 0 bit 1 r/w dbgmode[0] 0 bit 0 r/w oe_dbg 0 this register is also accessible via the pci interface at address 0x00ff00a0. oe_dbg: if this bit is a logic 1, the dbg[2:0] outputs of the pm3351 drive valid logic levels; otherwise the dbg[2:0] outputs are high impedance. dbgmode[2:0]: these bits determine the content and format of the data presented on the dbg[2:0] outputs. dbgmode[2:0] 000 the dbg[2:0] outputs present which memory consumer currently has been granted access. the eight consumers are encoded as follows: dbg[2:0] 000 processor load unit 001 processor instruction fetch unit 010 dma 011 hostif (pci slave accesses) 100 hash 101 dpo (transfer ring support) 110 unused 111 unused 001 this mode allows the current program counter (pc) to be output simultaneously with a selected internal signal. the 22 most significant bits of the pc are serialized as 2-bit data on dbg[2:1]. the pc is transmitted starting with the least significant bits (pc[3:2]) and is shifted every sysclk period. the dbg[0] output presents the internal signal selected by the ssel[6:0] register bit. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 199 010 this mode allows the current program counter (pc) to be output with an alignment marker. the pc is output as described above for mode 001, but an active high pulse aligned to pc[3:2] is generated on the dbg[0] output. 011 this mode allows the current program counter (pc) to be output simultaneously with a selected internal signal. it differs from mode 001 in that only bits 11 through 2 of the pc are serialized as 2-bit data on dbg[2:1]. the pc is transmitted starting with the least significant bits (pc[3:2]) and is shifted every sysclk period until pc[11:10]. the dbg[0] output presents the internal signal selected by the ssel[6:0] register bit. 100 this mode allows the current program counter (pc) to be output with an alignment marker. the pc is output as described above for mode 011, but an active high pulse aligned to pc[3:2] is generated on the dbg[0] output. 101 - 111 reserved ssel[6:0]: the ssel bits select one of 128 internal signals for presentation on the dbg[0] output when oe_dbg is a logic 1 and dbgmode[2:0] is either 3'b001 or 3'b011. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 200 ssel signal ssel signal ssel signal 127 cop_cond[13] 84 mrf_valid 41 gpo[3] 126 cop_cond[12] 83 dpi_mcf_wen 40 gpo[2] 125 cop_cond[11] 82 dpi_mrf_ren 39 gpo[1] 124 mcfg_en 81 dpwen 38 gpo[0] 123 oe_erst 80 dpweof 37 gpi[12] 122 core_reset_ 79 dpi_learn_sa 36 gpi[11] 121 dporq 78 dpi_we1 35 gpi[10] 120 hmrq 77 dma_we1 34 gpi[9] 119 smrq 76 dma_we3 33 gpi[8] 118 dmrq 75 tx_ren 32 gpi[7] 117 imrq 74 tframe 31 gpi[6] 116 lmrq 73 tx_datainvalid 30 gpi[5] 115 hmrdy 72 txdsync_en 29 gpi[4] 114 smrdy 71 txf_set_transmit 28 gpi[3] 113 dmrdy 70 linkrframe 27 gpi[2] 112 imrdy 69 lrf_has_lastword 26 gpi[1] 111 lmrdy 68 dma2lrf_done 25 gpi[0] 110 sra_newaddr 67 dma_state_hit 24 cop_cond[10] 109 sra_active 66 linkren 23 cop_cond[9] 108 sra_done 65 flist_null 22 cop_cond[8] 107 sra_lastword 64 flist_lock 21 cop_cond[7] 106 swfvalid 63 gpo[29] 20 cop_cond[6] 105 srfwen 62 gpo[28] 19 cop_cond[5] 104 swfren 61 gpo[27] 18 cop_cond[4] 103 hwr 60 gpo[26] 17 cop_cond[3] 102 hrd 59 gpo[25] 16 cop_cond[2] 101 bkpt 58 gpo[24] 15 cop_cond[1] 100 merr 57 gpo[23] 14 cop_cond[0] 99 mperr 56 gpo[22] 13 intr[12] 98 rhalt 55 gpo[21] 12 intr[11] 97 rclk_en 54 gpo[20] 11 intr[10] 96 ramdis 53 gpo[19] 10 intr[9] 95 romdis 52 gpo[18] 9 intr[8] 94 req_lock 51 gpo[17] 8 intr[7] 93 holdoff_req_int 50 gpo[16] 7 intr[6] 92 req_present 49 gpo[15] 6 intr[5] pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 201 91 dpiprd_rq 48 gpo[14] 5 intr[4] 90 dpopwr_rq 47 gpo[10] 4 intr[3] 89 dpiprd_gt 46 gpo[9] 3 intr[2] 88 dpopwr_gt 45 gpo[7] 2 intr[1] 87 mwf_wen 44 gpo[6] 1 intr[0] 86 mcf_wen 43 gpo[5] 0 stall_ 85 mrf_ren 42 gpo[4] register 0x38 (cr24): dpi datadescriptor word 0, low (dpi_dd0l) bit type function default bit 15 to 0 r/w rdd0[15:0] 0 rdd0[15:0]: bits 15:0 of word 0 of data descriptor read over the pci expansion bus. register 0x39 (cr25): dpi datadescriptor word 0, high (dpi_dd0h) bit type function default bit 15 to 0 r/w rdd0[31:16] 0 rdd0[31:16]: bits 31:16 of word 0 of data descriptor read over the pci expansion bus. register 0x3a (cr26): dpi datadescriptor word 1, low (dpi_dd1l) bit type function default bit 15 to 0 r/w rdd1[15:0] 0 rdd1[15:0]: bits 15:0 of word 1 of data descriptor read over the pci expansion bus. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 202 register 0x3b (cr27): dpi datadescriptor word 1, high (dpi_dd1h) bit type function default bit 15 to 0 r/w rdd1[31:16] 0 rdd1[31:16]: bits 31:16 of word 1 of data descriptor read over the pci expansion bus. register 0x3c (cr28): dpi datadescriptor word 2, low (dpi_dd2l) bit type function default bit 15 to 0 r/w rdd2[15:0] 0 rdd2[15:0]: bits 15:0 of word 2 of data descriptor read over the pci expansion bus. register 0x3d (cr29): dpi datadescriptor word 2, high (dpi_dd2h) bit type function default bit 15 to 0 r/w rdd2[31:16] 0 rdd2[31:16]: bits 31:16 of word 2 of data descriptor read over the pci expansion bus. register 0x3e (cr30): dpi datadescriptor word 3, low (dpi_dd3l) bit type function default bit 15 to 0 r/w rdd3[15:0] 0 rdd3[15:0]: bits 15:0 of word 3 of data descriptor read over the pci expansion bus. register 0x3f (cr31): dpi datadescriptor word 3, high (dpi_dd3h) bit type function default bit 15 to 0 r/w rdd3[31:16] 0 rdd3[31:16]: bits 31:16 of word 3 of data descriptor read over the pci expansion bus. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 203 dpi functional block (dma transmit channel) the purpose of the dma transmit channel (dpi functional block) is to read a frame of data over the pci expansion bus. the switch processor writes the dpi_rddl and dpi_rddh registers with the address of the data descriptor that is to be read over the pci expansion bus. the dpi logic then reads the frame data across the pci expansion bus, packetbuffer-by-packetbuffer, automatically following the linked list of packetbuffers. if the learn bit in the data descriptor flags field is set, then a hash lookup is done on the source address of the ethernet frame (see description of hdpisrcl/m/h registers). both the data descriptor and the mac source address of the ethernet frame that has been read over the pci expansion bus are held in control registers. the dpi functional block generates an interrupt to the switch processor after the data descriptor and mac source and destination addresses have been read (transmitframe header in interrupt: dpi_hd_done). the nextdd field of the data descriptor is used by firmware to update the remdd field of the expansion port descriptor. the data portion of the packet buffers (typically a mac ethernet frame with the preamble and start-frame-delimiter stripped) is read by the dpi from the internal pci master read interface and writes the frame data into a data fifo that is part of the tx_fifo functional block. in order to limit the processing that needs to be done by the switch processor the dpi functional block is capable of initiating an acknowledge counter increment after the frame has been read over the pci expansion bus by interfacing directly with the transfer handshake channel. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 204 register 0x40 (cr32): dpi control/status register (dpi_ctrl) bit type function default 15 :14 unused 0 13 r no_pb 0 12:8 r s[4:0] 0 7 r/w unused 0 6 r/w enhpcirdmode 0 5 r/w en_dpi_ack 0 4 r/w en_dpi_learn_sa 0 3 r/w sel_dpi_dd 0 2 r/w dpi_dd_en 0 1 r/w dpi_hd_en 1 0 r/w dpi_done_en 0 no_pb: state bit that is set if the data descriptor that was read acros the pci expansion bus had a firstpb field of 24h0 (that is, the packetbuffer pointer is a null pointer). this bit is valid during the dpi header in interrupt (dpi_hd_done) and is cleared when the dpi state machine returns to idle (which occurs in-between reading of each frame). s[4:0]: internal state vector for the dpi functional block. present for observability. enhpcirdmode: if this bit is a logic 0 the dpi will read the entire packet buffers worth of data over the pci expansion bus. if this bit is logic 1 the dpi will implement a more efficient transfer protocol: an enhanced pci read mode. this is done in the following manner. if the number of packet buffers in the frame is greater than one (1) then it is expected that the first packet buffer header of the frame to be formatted in the following manner: bits [31:24] bits [23:0] word 0 size nextpb word 1 last_size don't care word 0 contains the normal information for the dpi. word 1 contains the number of bytes in the last packet buffer in this frame. the number of packetbuffers in the frame is pre-loaded from the numpbs field of the data pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 205 descriptor as it is loaded in the dpi_dd1h register. as each packetbuffer in the frame is read across the pci bus (the actual number of bytes read across the pci bus per packetbuffer is given by the rpbsize register), the count of remaining packetbuffers is decremented. when the count is 1 (indicating that this is the last packetbuffer), the number of bytes read across the pci bus is simply: (size + 8). the number 8 accounts for the 8-bytes in the header of each packetbuffer structure. en_dpi_ack: enable for dpi initiated acknowledge. if enabled, the dpi will initiate the acknowledge counter increment over the pci expansion bus without requiring intervention of the switch processor. en_dpi_learn_sa: enable for the feature to allow the dpi to initiate a hash lookup on the mac source address of a frame if the learn bit was set (1) in the data descriptor that was read over the pci expansion bus. sel_dpi_dd: the setting of this bit determines which of two possible interrupt conditions will be mapped to the dpi head-of-packet interrupt line (transmitframe header in interrupt: dpi_hd_done) that goes to the switch processor . one of two conditions can be selected. if sel_dpi_dd is clear (0): the interrupt is asserted when the data descriptor and the first 12 bytes of the first packetbuffer are read over the pci expansion bus (i.e. select the dpi_hd_intr signal as the source of the dpi_hd_done interrupt line). if sel_dpi_dd is set (1): the interrupt is asserted as soon as the data descriptor is read over the pci bus (i.e. select the dpi_dd_intr signal as the source of the dpi_hd_done interrupt). dpi_dd_en: this bit is used as an enable for the dpi_dd_intr signal. for the dpi_dd_intr to be logically asserted the dpi_dd_en bit must be set (1). dpi_hd_en: this bit is used as an enable for the dpi_hd_intr signal. for the dpi_hd_intr to be logically asserted the dpi_hd_en bit must be set (1). dpi_done_en: this bit is used as an enable for the dpi_done interrupt signal. for dpi_done interrupt to be logically asserted the dpi_done_en bit must be set (1). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 206 register 0x41(cr33): tx fifo write size register (at fifo tail) bit type function default bit 15 to 11 unused 0 bit 10 to 0 r/w txf_wsize 0 txf_wsize: txf_wsize control register: this is the number of valid data bytes that are in the frame written into the tx_fifo data ram (either via the dpi module or by the switch processor writing a management frame) -or- into the mac ctrl frame fifo. the size includes the 4-byte crc (regardless as to whether the crc was appended by the tx_fifo logic or was already present in the frame). register 0x42 (cr34): dpi remote datadescriptor address, low (dpi_rddl) bit type function default bit 15 to 0 r/w remdd[15:0] 0 remdd[15:0]: this is the low 16 bits of the pci address from which a data descriptor is to be read by the dpi. register 0x43 (cr35): dpi remote datadescriptor address, high (dpi_rddh) bit type function default bit 15 to 0 r/w remdd[31:16] 0 remdd[31:16]: this is the high 16 bits of the pci address from which a data descriptor is to be read by the dpi. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 207 tx_fifo functional block: the tx_fifo functional block is intended to be a "smart " datapath from the dpi to the mac 100-mbit link. it presents a fifo interface to the dpi and mac link functional blocks. this allows the dpi and mac link interfaces to operate independently. during frame transmission, the tx_fifo read interface (head of fifo which interfaces to the mac link transmit logic) will initiate re-transmission of the frame after collisions (assuming half-duplex configuration) if the disposition code of the frame is not changed (see below). a running tally of the size of frames being written to or read from the tx_fifo and being transmit on the mac link media is kept (txf_dsize, txf_wsize, and txf_rsize control registers). additionally, the transmitstatus of a frame that has been transmit (or has attempted to transmit) on the mac link media is held in an internal register and is valid during assertion of either the tx_done or collision interrupts to the switch processor (see txf_dsize register description). major components of the tx_fifo datapath 1. a 512_word x 36-bit data ram. this ram holds frame data which is to be transmitted by the mac link functional block. for normal data frame transmission, the dpi functional block transparently writes data into the tx_fifo data ram and the transmit interface of the mac link functional block reads data out of the data ram. the format of the data in the data ram is a 32-bit data word and a 4-bit byte-enable code. a byte-enable code of 4'h0 represents an end-of-frame delimiter. at the end of writing a frame into the data ram the tx_fifo hardware autonomously writes a pointer to the next endofframe delimiter. this is done to allow easy dropping of frames at the head of the fifo. 2. a 32_word x 4-bit disposition fifo (dsfifo). each and every frame in the tx_fifo data ram has associated with it a 4-bit disposition code. this code is written into the dsfifo either concurrent or after the frame has been written into the tx_fifo data ram. when the frame comes to the "head" of the tx_fifo data ram a state machine decodes the disposition code and takes appropriate action. 3. a 64-byte fifo that allows the switch processor to format and transmit a mac control frame (mcfifo). the tx_fifo allows both data frames and mac control frames to be transmit. a mulitplexer selects whether to transmit a mac control frame rather then a pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 208 data frame on the mac link. the switch processor can write the control frame to the mcfifo and then flip a bit to signal to the tx_fifo hardware that the frame is to be transmit from the mcfifo to the mac link. 4. support to allow the switch processor to write an ethernet frame to the tx_fifo data ram this is required for transmitting a "tx management frame"; that is a frame created by this pm3351 chip for transmission on the link media. firmware running on the switch processor is able to write a data frame to the tx_fifo along with its associated dsfifo disposition code. 5. support of firmware read of a frame from the tx_fifo. this is required for an "rx management frame". what makes an "rx management" type frame special from a hardware perspective is that the frame is expected to be read out of the tx_fifo data ram and will most likely not be transmitted on the link media. tx_fifo interrupts to switch processor 1. tx_done : the frame is done being transmitted on the link media without collision. this interrupt is conditional on the txf_csr.en_tx_done_intr bit being set. 2. txf_stop : a frame is at the head of the tx_fifo and has a disposition code of type "stop". disposition of frames: disposition of frames can be done at both the tail and the head of the tx_fifo datapath. this allows either a one-stage (disposition via dstail register only) or two- stage disposition (disposition first via dstail and second via dshead) of the frame. the interface provided for doing this is a simple control register interface. the dstail register writes disposition information into the dsfifo ram. each and every frame which is written into the tx_fifo data ram is required to have exactly one write to the dstail register. normal data frames only require dispositioning via a write to the dstail register. from a firmware perspective there are 16 possible disposition codes. the hardware decodes these 16 disposition codes are mapped into one of three types of hardware action codes: pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 209 transmit stop drop the dshead register is provided to allow a flexible, two-stage disposition of the frame. a frame that had a hardware action code of "stop" written into the dstail register will assert the txf_stop interrupt to the switch processor when the frame comes to the head of the fifo. the firmware routine for servicing txf_stop can then do the following: read the disposition code that was written when the frame was at the tail of the fifo (i.e. when the frame was being written into the tx_fifo data ram). firmware can read the contents of the frame, if so desired, from the tx_fifo data ram. the firmware can then modify the disposition code by writing a disposition code that maps to transmit or drop into the dshead fifo. this will result in the frame that had generated the txf_stop interrupt to be either transmitted or dropped. firmware restriction rules on writing the dstail and dshead registers: these rules apply for each frame which is written to the tx_fifo data ram, either by the dpi functional block (that is, a standard data frame read over the pci expansion bus) or by firmware (that is, a tx management frame). rule 1: under no conditions should the dshead control register be written to if the "txf_stop" interrupt is deasserted since this may yield an unrecoverable device error. rule 2: this rule, which follows from rule 1 but is restated for clarity, shows that only a frame with a stop code written into the dstail disposition register can be modified when the frame reaches the head of the tx_fifo data ram. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 210 sequence description for transmission of ethernet data frames. the frame is read over the expansion bus using the dpi channel on the pm3351. payload data from the frame is transparently written to the tx_fifo data ram as the linked-list of packetbuffers is read on the pci bus. after the data descriptor and the first 12-bytes of the frame have been read across the pci bus the "dpi_hd_done" interrupt line will be asserted. the firmware interrupt service routine writes one 4-bit disposition code into the dstail control register; this write will cause the disposition code to be loaded into the 32_wordx4-bit disposition fifo (dsfifo). for normal data frames this will be one of the seven firmware codes that map to "transmit". note that the "dpi_hd_done" interrupt line will become asserted concurrent to frame data being written to the tx_fifo data ram. if the txf_csr.fix_crc bit is set (1) and the frame that was written to the tx_fifo had an incorrect or missing crc, then a correct 4 byte "crc" is appended (that is, the correct 802.3 framechecksequence is appended). the frame will eventually make its way to the head of thetx_fifo data ram as frames ahead of it are either transmitted or dropped. when the frame reaches the head of the tx_fifo data ram the output state machine will read out the disposition code from the dsfifo to the dshead register. since the code in this example is a transmit code, the state machine will autonomously load the frame into the tx interface of the mac link functional block on a byte-by- byte basis. when the last byte of the frame has been successfully transmitted on the link media without experiencing a collision the tx_fifo will do one of two things depending on the setting of the txf_csr.en_tx_done_intr bit: if the en_tx_done_intr bit is set then the tx_fifo output state machine will enter a holding state until the gpo line "thaw_tx_done" is flipped. the tx_fifo output state machine will then return to the idle state, from whence it will read out the next available frame to transmit. if the en_tx_done_intr bit is clr then the tx_fifo output state machine will immediately return to idle. the tx_fifo output state machine leaves the idle state whenever there is at least one frame that is ready to be transmit from the tx_fifo data ram (the entire frame has been written into the tx_fifo data ram and has been dispositioned by writing to the dstail control register) or a mac control frame is ready for transmission. if during the course of the transmit a collision (half-duplex only) occurs the tx_fifo will hold in a state until the collision interrupt is serviced by the switch processor; this is done to allow the service routine for collision to change the disposition code in the pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 211 dshead control register from transmit to drop in the case of excess collisions (i.e. 16 consecutive collisions) and to update collision statistics. register 0x44 (cr36): tx_fifo control register (txf_csr) bit type function default bit 15 r/w unused 0 bit 14 r/w auto_inc_mode 1 bit 13 r/w sw_write_mode 0 bit 12 r/w frame_mode 0 bit 11 r/w bswp_rwdata 0 bit 10 r/w bswp_rrdata 0 bit 9 r/w wr_mcframe 0 bit 8 r/w rd_mcframe 0 bit 7 r/w en_txdone_intr 1 bit 6 r/w fix_crc 0 bits 5:0 r/w max_pkts[5:0] 0x1e auto_inc_mode: puts thetx_fifo into auto increment mode. this feature, if set (1), results in having various write and read pointers auto incremented for switch processor frame accesses to the data ram and mac control frame rams (that is, if the frame_mode bit is also set). this relieves firmware from having to keep track of the read and write pointers. affected ram address pointers: wr_ptr and rd_ptr (for tx_fifo data ram) and mcwptr (for mac ctrl frame ram). sw_write_mode: controls whether the txf_datah and txf_datal register is configured for read or write of either the tx_fifo data ram or mac ctrl ram. if this bit is set (1) then data written to the txf_datah/l registers will be written to the selected ram; if the bit is clear (0) then data read from the selected ram may be read by the switch processor in the txf_datah/l register. frame_mode: defines the type of access with respect to the data ram. if this bit is set (1) then write accesses to the tx_fifo data ram by the switch processor are taken to be ethernet frame data and are formatted in the rams accordingly. if this bit is clear (0) then the switch processor may arbitrarily read and write bytes in either the data ram or the mac control frame ram. in normal switch applications this bit is set (1) during the firmware initialization sequence. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 212 bswp_rwdata: if set (1), then a byte-swap is performed data being written to the tx_fifo data ram by the switch processor. bswp_rrdata: if set (1), then a byte-swap is performed on data being read by the switch processor from the tx_fifo data ram. note: these two bswp bits are not intended to be used by the programmer and should be left in the default state, 0. instead, if a byte-swap is desired to be performed on ethernet frame data, use the epbe mode bit. if epbe mode bit is (1), the a byte-swap is performed on the ethernet frame data in the dpi module, which is prior to the tx_fifo in the transmit datapath. wr_mcframe: mode bit for selecting the ram that is the target of a switch processor write access. if set (1), then mac ctrl frame ram is target of write; if clear (0), target is tx_fifo data ram. rd_mcframe: mode bit for selecting the ram that is the target of a switch processor read access. if set (1), then mac ctrl frame ram is target of read; if clear (0), target is tx_fifo data ram. en_txdone_intr: if set (1), enables the tx_done interrupt to the switch processor at end of all frames successfully transmit on link media. if clear (0) the tx_done interrupt will never be asserted. fix_crc: if set (1) enables appending of a correct 802.3 framechecksequence (i.e. crc) at the end of every frame written to either the tx_fifo data ram or mac control frame ram if, and only if, the crc for the frame as it was originally written had an incorrect framechecksequence. if clear (0) no crc will be appended. note- if a crc is appended on the frame then the frame length will be increased by 4 bytes. however, no field in the ethernet frame (such as the length field of an 802.3 frame, is modified). example: if 60 bytes of frame data were written by the switch processor into the tx_fifo data ram but without a crc, and the fix_crc bit is set, then the tx_fifo logic will append a 4 byte crc and the final frame size will be 64-bytes. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 213 max_pkts[5:0]: this is the maximum number of packets that are allowed in the disposition fifo (dsfifo). the value in this register is compared to the number of valid entries in the dsfifo ram and is used to set a full threshold flag that is used by internal logic to hold off the dpi from fetching additional frames. this value default to decimal 30; the value in this register should not be written to be greater than 30. register 0x45 (cr37): tx_fifo read address pointer (txf_raddr) bit type function default bit 15 to 11 r/w mcrptr[6:2] 0 bit 10 to 0 r/w rd_ptr[10:0] 0 mcrptr[6:2]: this is the read pointer used for read access to the 64-byte mac control frame ram. mcrptr[6:0] is the byte address of the ram. rd_ptr[10:0]: this is the read pointer used for read access to the tx_fifo data ram. rd_ptr[10:0] is the byte address of the data ram. note- in normal operation the mcrptr and rd_ptr registers are not intended to be written. writing these registers during switch operation can cause data transmit errors on the mac transmit link interface. register 0x47 (cr39): transmit frame status register (txf_dsize) bit type function default bit 15 r txlong 0 bit 14 r deferred_tx 0 bit 13 to 11 r unused 0 bit 10 to 0 r txsize 0 the transmit frame status register holds information on a frame that has been successfully transmit on the link media (that is, if in half-duplex there was no collision). the contents of this register are valid for access by the switch processor when the tx_done interrupt is asserted. the transmit datapath is pipelined to allow for full- throughput on the mac link interface: tx_done interrupt can be asserted for transmit frame #n while the mac link interface is transmitting data on the mii for frame #(n+1). pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 214 txlong: this bit is set (1) if the frame that was read out of the tx_fifo had a frame size greater thant the maximum frame size control register (see link constant register max_size). the transmit frame will be truncated to be exactly max_size number of bytes on the link media. deferred_tx: this bit is set (1) if the frame transmission attempt was deferred. note C this bit is set by hardware regardless as to whether the deference occurred during the first or subsequent transmission attempt. for support of the ethernet mib statistic statsdeferredtransmissions the switch processor must qualify this bit by first transmission attempt and not a collision. txsize: this is the number of bytes that were successfully transmit on the mac link media (the mii interface). the value of this register can be used for maintenance of ethernet byte transmit statistics and is valid during assertion of the tx_done interrupt. register 0x48 (cr40): tx_fifo switch processor read/write data register, low (txf_datal) bit type function default bit 15 to 0 r/w swdata[15:0] 0 register 0x49 (cr41): tx_fifo switch processor read/write data register, high (txf_datah) bit type function default bit 15 to 0 r/w swdata[31:16] 0 swdata[31:0]: this register pair is used by the switch processor for access to the tx_fifo data ram and the mac control frame ram. the mode (read versus write), is set via the sw_write_mode bit in the txf_csr register. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 215 register 0x4a (cr42): tx_fifo valid byte register (txf_valid) bit type function default bit 15 to 12 r ostate[3:0] 0 bit 11 to 8 r istate[3:0] 0 bit 7 to 4 r rvalid[3:0] 0 bit 3 to 0 r/w wvalid[3:0] 0 ostate[3:0]: this read-only register gives the value of the ostate state machine in the tx_fifo module. istate[3:0]: this read-only register gives the value of the istate state machine in the tx_fifo module. rvalid[3:0]: this read-only register gives the value of the valid bit field of the tx_fifo data ram. the tx_fifo data ram is 36-bits wide. during switch processor read of the tx_fifo data ram the txf_datal and txf_datah control registers will return the low 32-bits of data (typically ethernet frame data) while the upper 4-bits of the data ram can be read from rvalid[3:0]. the rvalid[3:0] bit-field codes are follows: an endofframe delimiter is given by the code 4h0 a valid byte enable pattern corresponding to four (code 4b1111), three (code 4b1110), two (code 4b1100), or one (code 4b1000) byte. this is the number of valid bytes in the data-word that is being read from the tx_fifo data ram. all other rvalid[3:0] code combinations are illegal. wvalid[3:0]: this register is written during switch processor writes to the tx_fifo data ram with the number of bytes that are valid in the next data-word that is written to the data ram via writes to the txf_datal and txf_datah control register. the write to the data ram occurs on the cycle following the write to the txf_datah register. therefore the txf_valid register must be set with the correct number of bytes in the data-word before the txf_datah register is written during switch processor frame writes. only the last data-word in a frame may have a wvalid[3:0] value that is less than or equal to 4h4. legal values of wvalid[3:0] are 4h1, 4h2, 4h3, and 4h4. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 216 register 0x4b (cr43): packet buffer size (in bytes) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w pbsize[7:0] d80 pbsize[7:0]: the value of pbsize[7:0] is interpreted by the hardware to be the size, in bytes, of the packet buffer in the local memory of the pm3351 device. this number is a constant that may be set to a value other than the default value of decimal 80 during initialization. one restriction is that the size must be an integer mulitple of 4. register 0x4c (cr44): packet buffer size (in bytes) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w rpbsize[7:0] d80 rpbsize[7:0]: the value of rpbsize[7:0] is interpreted by the hardware to be the size, in bytes, of the packet buffer that is to be read across the pci expansion bus as part of the frame transfer protocol. this number is a constant that may be set to a value other than the default value of decimal 80 during initialization. one restriction is that the size must be an integer mulitple of 4. dpo funtional block (dma transfer handshake channel) the dpo functional block is the name of the hardware that supports the eight transfer rings that are associated with each of the eight possible devices in an elan 1x100 or elan 8x10 system. the switch processor sets up the linked list of blank data descriptor structures that are used for the transfer rings at initialization and then the dpo channel is responsible for: transfer ring management (read and write pointer) generating the master write commands (all single word bus transactions) that increment the request and acknowledge counters on elan-compatible chips over the pci expansion bus pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 217 the switch processor writesa template data descriptor to control registers in the dpo module. the dpo channel is responsible for replicating this data descriptor in local memory in the transfer ring for each chip to which the frame is to be switched. de-allocation of the data descriptor associated with a frame that has been acknowledged. the dpo functional block does not in any way modify or interpret the template data descriptor that is written by the switch processor to the control registers. register 0x4d (cr45): dpo: pci increment counter write data, low (ipcidatal) bit type function default bit 15 to 0 r/w ipcidata[15:0] 0 register 0x4e (cr46): dpo: pci increment counter write data, high (ipcidatah) bit type function default bit 15 to 0 r/w ipcidata[31:16] 0 ipcidata[31:0]: the contents of this register pair is used as the data-word during the pci bus transaction that is used by the pm3351 for the single-word writes to the request and acknowledge counters on the pci expansion bus. the present implementation of the elan protocol does not make use of the actual data that is in the data-word during the pci bus transaction that increments the request and acknowledge counters. this register is provided to allow for extensions to the basic protocol in special applications. register 0x4f (cr47): dpo: transfer handshake channel chip mask (ichip_mask) bit type function default bit 15 to 8 r dpo_af[7:0] 0 bit 7 to 0 r/w ichip_mask[7:0] 0 dpo_af[7:0]: almost-full flag for each of the eight transfer rings (with the bit index corresponding to the queue number). almost full occurs when the number of valid elements in the transfer ring is either greater than or equal to 1 less than the size of the ring. these register bits are provided for observability and should not be required for use by the switch processor during normal frame switching. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 218 ichip_mask[7:0]: this chip mask is written by the switch processor to indicate to the dpo hardware the transfer rings on which the frame is to be appended. each bit index of the mask corresponds to the transfer ring number. so a unicast frame will have one bit set (1) in ichip_mask[7:0] whereas a broadcast frame will have (n-1) bits set in ichip_mask[7:0], where n is the total number of elan-compatible chips attached to the pci expansion bus. register 0x50 (cr48): dpo: transfer handshake channel data descriptor word 0, bits [15:0] (idd0l) bit type function default bit 15 to 0 r/w idd0[15:0] 0 idd0[15:0]: template data descriptor word #0, bits [15:0], written by switch processor. register 0x51 (cr49): dpo: transfer handshake channel data descriptor word 0, bits [23:16] (idd0h) bit type function default bit 15 to 12 r s[3:0] 0 bit 11 to 8 unused 0 bit 7 to 0 r/w idd0[23:16] 0 s[3:0]: dpo functional block state. idd1[23:16]: template data descriptor word #0, bits [23:16], written by switch processor. register 0x52 (cr50): dpo: transfer handshake channel data descriptor word 1, bits [15:0] (idd1l) bit type function default bit 15 to 0 r/w idd1[15:0] 0 idd1[15:0]: template data descriptor word #1, bits [15:0], written by switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 219 register 0x53 (cr51): dpo: transfer handshake channel data descriptor word 1, bits [23:16] (idd1h) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd1[23:16] 0 idd1[23:16]: template data descriptor word #1, bits [23:16], written by switch processor. register 0x54 (cr52): dpo: transfer handshake channel data descriptor word 2, bits [15:0] (idd2l) bit type function default bit 15 to 0 r/w idd2[15:0] 0 idd2[15:0]: template data descriptor word #2, bits [15:0], written by switch processor. register 0x55 (cr53): dpo: transfer handshake channel data descriptor word 2, bits [23:16] (idd2h) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd2[23:16] 0 idd2[23:16]: template data descriptor word #2, bits [23:16], written by switch processor. register 0x56 (cr54): dpo: transfer handshake channel data descriptor word 3, bits [15:0] (idd3l) bit type function default bit 15 to 0 r/w idd3[15:0] 0 idd3[15:0]: template data descriptor word #3, bits [15:0], written by switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 220 register 0x57 (cr55): dpo: transfer handshake channel data descriptor word 3, bits [23:16] (idd3h) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd3[23:16] 0 idd3[23:16]: template data descriptor word #3, bits [23:16], written by switch processor. register 0x58(cr56): dpo: transfer handshake channel data descriptor word 0, bits [31:24] (idd0flag) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd0[31:24] 0 idd0[31:24]: template data descriptor word #0, bits [31:24], written by switch processor. register 0x59(cr57): dpo: transfer handshake channel data descriptor word 1, bits [31:24] (idd1flag) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd1[31:24] 0 idd1[31:24]: template data descriptor word #1, bits [31:24], written by switch processor. register 0x5a(cr58): dpo: transfer handshake channel data descriptor word 2, bits [31:24] (idd2flag) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd2[31:24] 0 idd2[31:24]: template data descriptor word #2, bits [31:24], written by switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 221 register 0x5b(cr59): dpo: transfer handshake channel data descriptor word 3, bits [31:24] (idd3flag) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w idd3[31:24] 0 idd3[31:24]: template data descriptor word #3, bits [31:24], written by switch processor. register 0x5c(cr60): dpo: transfer handshake channel control/status register (ic_ctrl) bit type function default bit 15 r incr_req_op 0 bit 14 r incr_ack_op 0 bit 13 r dpi_incr_ack_ op 0 bit 12 r pending_req 0 bit 11 r ring_full 0 bit 10 to 9 r unused 0 bit 8 to 7 r/w ic_test_en[1:0] 0 bit 6 to 3 r/w regtype[3:0] 0 bit 2 to 0 r/w ringnum[2:0] 0 incr_req_op: status bit set if dpo is actively performing an operation to increment the request counter across the pci expansion bus. incr_ack_op: status bit set if dpo is actively performing an operation to increment the request counter across the pci expansion bus and it was the switch processor that initiated the operation. dpi_incr_ack_op: status bit set if dpo is actively performing an operation to increment the request counter across the pci expansion bus and it was the dpi functional block that initiated the operation. in normal operation the firmware will usually only select one method for initiating the increment of the acknowledge counter. having the dpi module initiate the acknowledge operation is more efficient. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 222 pending_req: this is an internal state bit that is set (1) if the switch processor wanted to initiate an increment request counter operations but the dpo state machine was not presently in state idle (which would occur if the dpo module was doing an increment acknowledge operation that was initiated by the dpi functional block). present for observability. ring_full: this status bit is set (1) if any of the eight possible transfer rings are full. ic_test_en[1:0]: these two register bits are for factory test and should not be set during normal operation. regtype[3:0]: windowed address type field. this is the address that is used for accessing one of ten possible windowed registers in the dpo module. 4d0: ic_mwen[15:0] 4d1: chipbase[7:0] (one per transfer ring) 4d2: rbase[23:8] (one per transfer ring) 4d3: rsize[3:0] (one per transfer ring) 4d4: wptr[15:0] (one per transfer ring) 4d5: rptr[15:0] (one per transfer ring) 4d6: ircountl[15:0] 4d7: ircounth[7:0] 4d8: iacountl[15:0] 4d9: iacounth[7:0] ringnum[2:0]: windowed register ring select. for windowed registers that are implemented on a per transfer ring basis, the value of this register selects the ring to be accessed. dpo windowed register description there are a total of 45 windowed registers that can be accessed in the dpo module: 40 of those registers are implemented as a set of 5 registers per transfer ring while 5 of those registers are implemented in the top-level dpo functional block. the dpo functional block windowed register address is decoded from the regtype[3:0] field of the ic_ctrl register while the ring number is decoded from the ringnum[2:0] field of the ic_ctrl register. the ic_data register is used as the data register for access to the dpo windowed registers. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 223 for example, if ringnum is 3h5 and regtype[3:0] is 4h3 then the rsize[3:0] register of ring #5 is can be accessed via the ic_data control register. following is the description of the windowed registers. bit type function default bit 15 to 0 r/w ic_mwen[15:0] 0 ic_mwen[15:0 (dpo windowed)]: write enable mask that is used for writing out the template data descriptor (which is in idd0[31:0] to idd3[31:0]. each bit is used to qualify one byte in the data descriptor. bit index 0 corresponds to idd0[7:0] and bit index 15 corresponds to idd3[31:24]. bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w chipbase[7:0] 0 chipbase[7:0] (dpo windowed: one per transfer ring): this is the slave base address (that is, the value of ad[31:24] on the pci bus during the address phase) of the device corresponding to this transfer ring. set during initialization by the switch processor and then not modified. bit type function default bit 15 to 0 r/w rbase[23:8] 0 rbase[23:8] (dpo windowed: one per transfer ring): pointer in local memory to the base of the transfer ring. the low 8 bits of the base address are hardwired to 8h0. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 224 bit type function default bit 15 to 4 r unused 0 bit 3 to 0 r/w rsize[3:0] 0 rsize[3:0] (dpo windowed: one per transfer ring): size of the transfer ring. this register value must be static during switch operation and is initialized by the switch processor. value size of ring 4d0 32 4d1 64 4d2 128 4d3 256 4d4 512 4d5 1024 (1k) 4d6 2048 (2k) 4d7 4k 4d8 8k 4d9 16k 4d10 32k 4d11 64k 4d12 64k 4d13 64k 4d14 64k 4d15 64k where size of the ring is given in terms of the number of data descriptors that are in the ring (which also corresponds to the maximum number of frames that can be queued up for transmit to the device to which this ring is assigned). bit type function default bit 15 to 0 r/w wptr[15:0] 0 wptr[15:0] (dpo windowed: one per transfer ring): this register holds the pointer in local memory that is used for writing data descriptors. in normal switch operation it is not accessed by the switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 225 bit type function default bit 15 to 0 r/w rptr[15:0] 0 rptr[15:0] (dpo windowed: one per transfer ring): this register holds the pointer in local memory that is used for reading data descriptors. in normal switch operation it is not accessed by the switch processor. bit type function default bit 15 to 0 r/w ircount[15:0] 0 ircount[15:0] (dpo windowed): bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w ircount[23:16] 0 ircount[23:16] (dpo windowed): this register holds the low 24-bits of the pci address that is to be used during an incrementing request counter operation. the high eight bits of the pci address are taken from the rbase[7:0] register of the applicable transfer ring. bit type function default bit 15 to 0 r/w iacount[15:0] 0 iacount[15:0] (dpo windowed): bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w iacount[23:16] 0 iacount[23:16] (dpo windowed): this register holds the low 24-bits of the pci address that is to be used during an incrementing acknowledge counter operation. the high eight bits of the pci address are taken from the rbase[7:0] register of the applicable transfer ring. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 226 register 0x5d (cr61): dpo: ring data access register, bits (ic_data) bit type function default bit 15 to 0 r/w ic_data[15:0] 0 ic_data[15:0]: this is the data register used for access to the windowed registers in the dpo functional block. the access to this register by the switch processor determines whether the register access is a read or a write. if the switch processor writes this register (via the ldi or move instructions) the write will propagate to the selected windowed register in the following cycle. register 0x5e (cr62): tx_fifo: disposition fifo, tail register (dstail) bit type function default bit 15 to 14 r unused 0 bit 13 to 8 r dscntr[5:0] 0 bit 7 to 4 r unused 0 bit 3 to 0 r/w dstail[3:0] 0 dscntr[5:0]: number of valid entries in the tx_fifo disposition fifo. dstail[3:0]: the switch processor writes this register with the disposition code of the frame that is being written into the tx_fifo data ram. register 0x5f (cr63): tx_fifo: disposition fifo, head register (dshead) bit type function default bit 15 to 14 r unused 0 bit 13 to 8 r framecntr[5:0] 0 bit 7 to 4 r unused 0 bit 3 to 0 r/w dshead[3:0] 0 framecntr[5:0]: number of frames that are in the tx_fifo data ram. during normal switch operation, this counter is incremented when the dpi module finishes reading a frame across the pci expansion bus and writing it out to the tx_fifo data ram. the counter is decremented after the frame is completed at the head of the fifo, either by being successfully transmit on pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 227 the mac link media or by being dropped from the data ram (which is only done under control of the switch processor). dshead[3:0]: this is the disposition code of the frame that is at the head of the tx_fifo data ram (that is, it is the code of the frame that either has been or will be read out of the tx_fifo data ram). this code is loaded by the tx_fifo hardware from the internal disposition fifo when it has been determined that a frame can be read out of the tx_fifo data ram. if the code in the register is mapped to a stop disposition code, an interrupt (txf_stop) will be issued to the switch processor. the switch processor can write this register with a code corresponding to transmit or drop after it has completed its processing the frame. note- this register can be written by the switch processor only if the txf_stop interrupt line is asserted; writing to this register at other times may cause an unrecoverable transmit error. register 0x60 (cr64): link constant register address (lc_sel) bit type function default bit 15 to 4 r unused 0 bit 3 to 0 r/w lc_sel[3:0] 0 lc_sel[3:0]: selects the address of the windowed register in the link functional block that is to be accessed via lc_data. value register accessed 4d0 ifs1_time 4d1 ifs2_time 4d2 pre_size 4d3 jam_size 4d4 max_size 4d5 min_size 4d6 blind_time 4d7 lbk_byte 4d8 lnstat2 4d9 etype 4d10 late_time 4d11 txcount pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 228 register 0x65 (cr65): link constant register data (lc_data) bit type function default bit 15 to 0 r/w lc_data[15:0] 0 lc_data[15:0]: this is the data register used for access to the windowed registers in the link functional block. the access to this register by the switch processor determines whether the register access is a read or a write. if the switch processor writes this register (via the ldi or move instructions) the write will propagate to the selected windowed register in the following cycle. link windowed register description there are a total of 11 windowed registers that can be accessed in the link functional block. each of these 11 registers holds data that is expected to be static (that is constant) during switch operation; they are expected to be accessed by the switch processor only during initialization. the link functional block windowed register address is decoded from the lc_sel register while the lc_data register is used as the data register. following is the description of the windowed registers in the link functional block. ifs1_time (link windowed register): bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w ifs1_time_reg[ 7:0] 8d13 ifs1_time_reg[7:0]: the value of this register determines the interframe spacing, part 1 (ifs1) that is used for transmission on the link media. the units of this register is in terms of nibble_times (that is, tx_clk cycles). the actual value of ifs1, in bit times is given by: ifs1 (bit times) = 4*(ifs1_time_reg + 2) pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 229 ifs2_time (link windowed register): bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w ifs2_time_reg[ 7:0] 8d6 ifs2_time_reg[7:0]: the value of this register determines the interframe spacing, part 2 (ifs2) that is used for transmission on the link media. the units of this register is in terms of nibble-times (that is, tx_clk cycles). the actual value of ifs2, in bit times is given by: ifs2 (bit times) = 4*(ifs2_time_reg + 3) pre_size (link windowed register): bit type function default bit 15 to 8 r unused 0 bit 7 to 0 r/w pre_size[7:0] 8d52 pre_size[7:0]: this register gives the number of bits of preamble that is used during transmit on the link media. the units are in bit-times. the value in this register must be set so that bits [1:0] are equal to 0. the actual number of preamble bits during transmission excluding the startframedelimiter is equal to: num_preamble_bits = 4*(pre_size + 1) note- the transmit link state machine always is guaranteed to insert a valid one-byte startframedelimiter. jam_size (link windowed register): bit type function default bit 15 to 12 unused 0 bit 11 to 0 r/w jamsize[11:0] 0x004 jamsize[11:0]: the length of a jam sent after a collision in byte times . so the default setting corresponds to a jam of 32 bits. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 230 max_size[11:0] (link windowed register): bit type function default bit 15 to 12 unused 0 bit 11 to 0 r/w maxsize[11:0] d1518 maxsize[11:0]: number of bytes at which an outgoing frame is truncated, and the number of bytes beyond which an incoming frame is considered to be long. for transmit, if a frame in the tx_fifo data ram has more bytes than given by maxsize the frame will be truncated to be exactly maxsize bytes and the txlong status bit in the txf_dsize register will be set (1). for receive, frames that are received on the mac link interface that are greater in size than maxsize will be truncated to exactly maxsize bytes (which will be written out to local memory in a linked-list of packetbuffers as is done for non-errored receive frames), the rxlong status bit in the dmstat1 register will be set (1), and the receive frame error interrupt line (rxerr_int) will be asserted to the switch processor. min_size[7:0] (link windowed register): bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w minsize[7:0] d64 minsize[7:0]: number of bytes below which a frame is considered to be short. this register is not used for transmit frames. if a frame is received on the mac link media with a frame size of less than minsize number of bytes the rxshort bit in the dmstat1 register will be set (1), and the receive frame error interrupt line (rxerr_int) will be asserted to the switch processor. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 231 blind_time (link windowed register): bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w blind[7:0] 0 blind[7:0]: blind time in nibble-times . this is the number of rx_clk times for which the link receiver is blinded after a transmit. the blind timer is not qualified by the duplex mode setting of the link (so for full-duplex operation this register is expected to be set to 0 by the switch processor). lbk_byte (link windowed register): bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w lbkbyte[7:0] 0x69 lbkbyte[7:0]: used by the link as the transmission data when in loopback mode. this data byte is continuously transmit as the data after a valid preamble and startframedelimiter has been sent. lnstat2 (link windowed register): bit type function default bit 15 r sticky_txlate col 0 bit 14 r sticky_rxfifo _ovrun 0 bit 13 r sticky_lrfifo_ ovrun 0 bit 12 to 8 r linkrwords[4: 0] 0 bit 7 to 5 r rx_if_sm[2:0] 0 bit 4 to 0 r tx_if_sm[4:0] 0 sticky_txlatecol: sticky error flag- late collision experienced during frame transmit. a late collision is one in which the link is configured for half-duplex and the col signal is asserted after more than a user-configurable number of bytes pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 232 of frame data have been framed on the mii interface pins (see late_time link windowed register). note- three sticky error flags are implemented. the flags can be cleared by setting the clr_sticky bit in the lnctrl register. sticky_rxfifo_ovrun: sticky error flag- fifo overrun occurred on the rxfifo of the link receiver functional block. sticky_lrfifo_ovrun: sticky error flag- fifo overrun occurred on the lrf fifo of the link receiver functional block. linkrwords[4:0]: this is the number of valid words in the link lrf fifo. present for observability. rx_if_sm[2:0]: value of receive interface state machine (present for observability). tx_if_sm[4:0]: value of transmit interface state machine (present for observability). etype (link windowed register): bit type function default bit 15 to 0 r/w etype[15:0] 0x8808 etype[15:0] the value of this register is compared to the value of the ethernet length/type field of a received frame. if the values match (that is, all bits are equal) then the receive frame status bit ctrl_frame is asserted: this status bit is mapped in the pm3351 to one of the gpi lines of the switch processor. late_time (link windowed register): bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w latetime[7:0] d56 latetime[7:0]: the number of bytes after the start of a frame after which a collision is pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 233 considered late. in full duplex operation the contents of this register have no effect. txcount (link windowed register): bit type function default bit 15 to 0 r txcount[15:0] 0 txcount[15:0]: transmit counter value. this counter is in the link transmit interface functional block and is present for testing purposes only. hash functional block the hash functional block on the pm3351 is capable of storing the results of three separate mac address hash searches. the result of each search and the pointers to the hash buckets can be read by the switch processor by accessing control registers. the mac address keys are also readable and writeable by the switch processor (although in normal operation they will not be written by the switch processor but by other internal hardware blocks that delimit the mac addresses from the ethernet frame). fail and busy status bits are supplied for each result and are mapped to separate gpi bits of the switch processor. on the pm3351 a hash search is done on the following three mac addresses: mac source address on link receive frames (search always done) mac destination address on link receive frames (search always done) mac source address on frames read across the pci expansion bus (search is initiated by the dpi logic if and only if the learn bit in the data descriptor flags field is set). in normal switch operation a hash search occurs as follows. the dma logic delimits the 48-bit mac address in the ethernet frame and writes it to the mac address control register. the 48-bit mac address is logically xored and anded with a mask register to form a 16-bit hash index: hash_index[15:0] = hmask[15:0] & (mac_addr[47:32] ^ mac_addr[31:16] ^ mac_addr[15:0]); the 16-bit hash index is used as an index into the hash array, where hmask is a control register which is set according to the size of the hash table. the hash search begins after the full mac address has been written to the control registers. during the hash search the linked-list of hash buckets and/or forwarding tags is scanned until pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 234 either the end-of-list is reached or a match is made on the mac address. while the hash search is in progress a busy status bit is asserted. after the hash search is complete, the busy signal is de-asserted and the pointer to the matching hash data structure is loaded to the applicable result control register. flow control is provided to the switch processor via hardware so that for each of the three possible mac address searches only one hash search will be active (for example, there will at most be one mac source address hash search busy; the dma will not attempt to initiate a second search until the previous search has completed and the switch processor has read the applicable control registers for the hash search). the switch processor can read the result of the hash search by reading the applicable hash result register. the pass/fail status on the search is available for the switch processor by testing a gpi line. each hash result register returns a different value depending upon whether the hash search passed or failed: a pass corresponds to a match in the mac address. the hash result register returns a pointer in local memory to the hash bucket or forwarding tag that has the 48-bit mac address equal to the address in the mac address key. a fail corresponds to the situation that the entire linked-list of hash buckets and/or forwarding tags corresponding to the hash array was traversed and the end-of-list was reached. the hash result register returns the pointer in local memory to the first node in the hash array for this index to which a new address can be attached (that is, it is the end of the linked-list for this hash index). register 0x62 (cr66): hash logic control/status register (hashctrl) bit type function default bit 15 r idle 1 bit 14 r/w en_idle 0 bit 13 to 3 unused 0 bit 2 r/w hctrl_hpsen 0 bit 1 r/w hdsen 0 bit 0 r/w hdden 0 idle: hash functional state machine in idle state. en_idle: if this bit is set (1) then the hash state machine will be prevented from leaving the idle state. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 235 hctrl_hpsen: enable bit for allowing the switch processor to initiate a hash search on the mac source address for a frame read across the pci expansion bus. hdsen: enable bit for allowing a hash search on the mac source address for a frame received on the link interface. hdden: enable bit for allowing a hash search on the mac destination address for a frame received on the link interface. in normal switch operation the firmware will leave the en_idle and hctrl_hpsen bits in their default state (0), and will set the hdsen and hdden bits (1). register 0x63 (cr67): hash mask register (hmask) bit type function default bit 15 to 0 r/w hmask[15:0] 0 hmask[15:0]: the contents of this register is used as a mask in the generation of the 16-bit hash index. register 0x64 (cr68): hash array base, address [15:0] (hbasel) bit type function default bit 15 to 2 r/w hbase[15:2] 0 bit 1 to 0 r hbase[1:0] 0 register 0x65 (cr69): hash array base, address [23:16] (hbaseh) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w hbase[23:16] 0 hbase[23:0]: this is the base address of the hash pointer array in local memory. the low two bits, indices 1:0, are hardwired to 2h0. register 0x66 (cr70): hash result register: dpi source address look-up, low (hdpisrcrl) pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 236 bit type function default bit 15 to 2 r/w hdpisrcr[15:2] 0 bit 1 to 0 r hdpisrcr[1:0] 0 register 0x67 (cr71): hash result register for dpi source address look-up, high (hdpisrcrh) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w hdpisrcr[23:16] 0 hdpisrcr[23:0]: hash result register for mac source address on frames read across the pci expansion bus (via dpi functional block). register 0x68 (cr72): hash result register: link rx frame destination address look-up, low (hdmadstrl) bit type function default bit 15 to 2 r/w hdmadstr[15:2] 0 bit 1 to 0 r hdmadstr[1:0] 0 register 0x69 (cr73): hash result register: link rx frame destination address look-up, high (hdmadstrh) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w hdmadstr23:16 ] 0 hdmadstr[23:0]: hash result register for mac destination address on link receive frames. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 237 register 0x6a (cr74): hash result register: link rx frame source address look-up, low (hdmasrcrl) bit type function default bit 15 to 2 r/w hdmasrcr[15:2] 0 bit 1 to 0 r hdmasrcr[1:0] 0 register 0x6b (cr75): hash result register: link rx frame source address look-up, high (hdmasrcrh) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w hdmasrcr23:16 ] 0 hdmasrcr[23:0]: hash result register for mac source address on link receive frames. register 0x6c (cr76): hash dpi source mac address, low (hdpisrcl) bit type function default bit 15 to 0 r/w hdpisrc[15:0] 0 register 0x6d (cr77): hash dpi source mac address, middle (hdpisrcm) bit type function default bit 15 to 0 r/w hdpisrc[31:16] 0 register 0x6e (cr78): hash dpi source mac address, high (hdpisrcl) bit type function default bit 15 to 0 r/w hdpisrc[47:32] 0 hdpisrc[47:0]: this is the 48-bit address key corresponding to the mac source address for frames read across the pci expansion bus. in normal switch operation this register is written by the dpi functional block as the frame is read across the pci expansion bus. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 238 register 0x6f (cr79): hash link rx destination mac address, low (hdmadstl) bit type function default bit 15 to 0 r/w hdmadst[15:0] 0 register 0x70 (cr80): hash link rx destination mac address, middle (hdmadstm) bit type function default bit 15 to 0 r/w hdmadst[31:16] 0 register 0x71 (cr81): hash link rx destination mac address, high (hdmadsth) bit type function default bit 15 to 0 r/w hdmadst[47:32] 0 hdmadst[47:0]: this is the 48-bit address key corresponding to the mac destination address for frames received on the link interface. in normal switch operation this register is written by the dma functional block as the frame is being written out to a packet buffer in local memory. register 0x72 (cr82): hash link rx source mac address, low (hdmasrcl) bit type function default bit 15 to 0 r/w hdmasrc[15:0] 0 register 0x73 (cr83): hash link rx source mac address, middle (hdmasrcm) bit type function default bit 15 to 0 r/w hdmasrc[31:16] 0 register 0x74 (cr84): hash link rx source mac address, high (hdmasrch) bit type function default bit 15 to 0 r/w hdmasrc[47:32] 0 hdmasrc[47:0]: this is the 48-bit address key corresponding to the mac source address for frames received on the link interface. in normal switch operation this register is written by the dma functional block as the frame is being written out to a packet buffer in local memory. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 239 register 0x75 (cr85): link control register (lwctrl) bit type function default bit 15 to 11 r/w unused 0 bit 10 to 9 r/w test_backoff[ 1:0] 0 bit 8 r/w unused 0 bit 7 r/w fdplx 1 bit 6 r/w clr_sticky 0 bit 5 r/w force_jam 0 bit 4 r/w txdisable 1 bit 3 r/w rxdisable 1 bit 2 r/w rxflush 0 bit 1 r/w unused 0 bit 0 r tx_enable 0 test_backoff[1:0]: this register is implemented for factory test. it should be left in its default state otherwise. fdplx: full duplex mode bit. if set (1) the link functional block is configured for full- duplex operation; if clear (0) the link is configured for half-duplex. if the link is configured for full-duplex operation the mii signals col and crs are qualified internally in the pm3351 to be logically de-asserted. when changing the duplex mode from full-duplex to half-duplex the link functional block should be reset using the frst register. clr_sticky: when set (1) this bit clears the three sticky link flags: sticky_txlatecol, sticky_rxfifo_ovrun, sticky_lrfifo_ovrun. force_jam: when this bit is set (1) the transmit link interface will continuously transmit a nibble pattern of 4h5 on the mii txd[3:0] pins and have tx_en asserted. the jam pattern is sent regardless as to the state of col or crs and the setting of the duplex mode. the jam pattern is stopped being sent when the force_jam bit is cleared (0). txdisable: if this bit is set (1) then frame transmission will be halted on a frame boundary pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 240 (so if the link is presently attempting to transmit a frame then frame transmission will be halted at the end of the present attempt, regardless as to whether a collision occurs). frame transmission will be re-started only after the txdisable bit is cleared. rxdisable: if this bit is set (1) then frame reception is halted on a frame boundary. frame reception will be re-started only after the rxdisable bit is cleared. since a partial frame may have been received while the rxdisable bit was set, the rxflush bit can be set to flush the partial frame from the link receive fifo interface and rxdisable and rxflush can then be simultaneously de-asserted. rxflush: if this bit is set (1) then the link receive interface is synchronously reset. this bit must be clear (0) to enable frame reception. register 0x76 (cr86): link status register (lwstat) bit type function default bit 15 r collision 0 bit 14 r txlatecol 0 bit 13 r lt_txlong 0 bit 12 r tframe 0 bit 11 r txlatezone 0 bit 10 r tx_enable 0 bit 9 r tx_ready 0 bit 8 r linkrframe 0 bit 7 r lrf_has_last word 0 bit 6 r receiving 0 bit 5 r rx_ready_s 0 bit 4 r lr_ctrl_fram e 0 bit 3 r lr_fifo_ovrun 0 bit 2 r lr_rxlong 0 bit 1 r lr_rxshort 0 bit 0 r lr_misalign 0 collision: this is the value of the collision interrupt line. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 241 txlatecol: late collision occurred during transmit. valid when the collision interrupt is asserted. lt_txlong: link transmitting a frame having a size greater than the value of the max_size link control register. valid if tframe is asserted. this bit is latched in the txf_dsize register (which is valid when the tx_done interrupt is asserted). tframe: transmitting frame on the mii interface. txlatezone: this bit is set (1) if a frame is being transmit and the frame is in the late collision zone (see link control register late_col). tx_enable: transmit enable flow control bit (for observability). tx_ready: transmit enable flow control bit (for observability). linkrframe: internal framing signal used by link receiver to indicate to the dma functional block that a receive frame is in the lrf fifo. lrf_has_lastword: internal status signal- set (1) when the lrf fifo has the last word of a received frame. receiving: the link rx state machine is in a state corresponding to frame reception. rx_ready_s: the rx fifo (on the mii interface) is non-empty. lr_ctrl_frame: receive frame status: a frame is being received having an ethernet length/type field of the same value as the etype link control register. status signal latched and held in dmstat control register. lr_fifo_ovrun: receive frame status: a fifo over-run has occured in the link receiver during reception of this frame. status signal latched and held in dmstat control register. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 242 lr_rxlong: receive frame status: a frame is being received with a length greater than that of the max_size link control register value. status signal latched and held in dmstat control register. lr_rxshort: receive frame status: a frame is being received with a length less than that of the min_size link control register value. status signal latched and held in dmstat control register. lr_crc_err: receive frame status: a frame is being received having an incorrect 802.3 framechecksequence field (that is, a crc error).. status signal latched and held in dmstat control register. lr_misalign: receive frame status: this bit is set (1) if an odd number of framed data nibbles have been received on the mii receive interface and the the framing signal (that is, the mii signal rx_dv) has become deasserted. status signal latched and held in dmstat control register. register 0x77 (cr87): link backoff counter (lwback) bit type function default bit 15 to 10 unused 0 bit 9 to 0 r/w backoff[9:0] 0 backoff[9:0]: link backoff register. this register is in units of slot times in which to backoff. this register is pre-loaded by the switch processor with the next backoff time to be used. the link transmit logic loads the value of this register into the txcount counter after the collision jam sequence has been sent (so half- duplex mode only). register 0x78 (cr88): number of packetbuffers (lwnbufs) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w lwnbuffs[7:0] 0 lwnbuffs[7:0]: the number of packetbuffers in the receive frame. valid when either receive frame interrupt is asserted to the switch processor (rx_frame or pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 243 rx_err_frame). in normal operation, this register is written by the dma and read by the switch processor. register 0x79 (cr89): first pb address low (lwfirstl) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w lwfirst[23:16] 0 register 0x7a (cr90): first pb address high (lwfirsth) bit type function default bit 15 to 0 r/w lwfirst[15:0] 0 lwfirst[23:0]: pointer (that is, the local memory address) of the first packetbuffer in the received frame. valid during assertion of a receive frame interrupt. register 0x7b (cr91): last pb address low (lwlastl) bit type function default bit 15 to 8 unused 0 bit 7 to 0 r/w lwlast[23:16] 0 register 0x7c (cr92): last pb address high (lwlasth) bit type function default bit 15 to 0 r/w lwlast[15:0] 0 lwlast[23:0]: pointer (that is, the local memory address) of the last packetbuffer in the received frame. valid during assertion of a receive frame interrupt. register 0x7d (cr93): link receive frame size (lwdsize) bit type function default bit 15 to 12 unused 0 bit 11 to 0 r/w rxsize[11:0] 0 rxsize: receive frame byte counter. this is the number of framed data octets on the link media (the mii interface). valid during assertion of a receive frame interrupt. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 244 register 0x7e (cr94): dpo: acknowledge pointer for transfer ring (ackrptr) bit type function default bit 15 to 0 r ackrptr[15:0] 0 ackrptr[15:0]: acknowledge pointer for transfer ring. the value of this register is used by the switch processor to compute the address in local memory of a data descriptor during an acknowledge interrupt service routine. one of eight transfer rings is selected depending on the value of the ackid_num[2:0] field in the ackid control register. the ackrptr[15:0] register returns the read pointer of the selected transfer ring. register 0x7f (cr95): tx_fifo read size register (txf_rsize) bit type function default bit 15 to 11 unused 0 bit 10 to 0 r/w txf_rsize[10:0] 0. txf_rsize[10:0]: this register holds the number of bytes that are being read out of either the tx fifo data ram or the tx fifo mac control frame ram. for data frames (that is, those being read out of the tx fifo data ram) that are transmit on the link media without collision the value of this register is latched and held in the txf_dsize register (which is valid during assertion of the tx_done interrupt). if a collision occurs during half-duplex transmission, then txf_rsize holds the number of bytes of data read out before the link transmit interface sensed the assertion of the mii col signal. if the txf_stop interrupt is asserted then this register holds the number of valid data bytes in the frame. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 245 interrupts to swtich processor the interrupt lines that are mapped to the switch processor on the pm3351 are prioritized in terms of the interrupt number, with int 0 (reset_vector) being the highest priority and int 15 (alarm2) the lowest priority. switch processor interrupt memory location intr bus index (rtl code) int 0 reset_vector 0x00 - int 1 alarm1 0x10 - int 2 rx_frame 0x20 intr[0] int 3 rx_err_frame 0x30 intr[1] int 4 tx_done 0x40 intr[2] int 5 collision 0x50 intr[3] int 6 txf_stop 0x60 intr[4] int 7 rpcim_done 0x70 intr[5] int 8 dpi_done 0x80 intr[6] int 9 dpi_hd_done 0x90 intr[7] int 10 ack_int 0xa0 intr[8] int 11 flist_err 0xb0 intr[9] int 12 req_int 0xc0 intr[10] int 13 mintr 0xd0 intr[11] int 14 task_intr 0xe0 intr[12] int 15 alarm2 0xf0 - reset_vector: this interrupt vector is taken after assertion of either a hardware (that is, assertion of the rst_ input pin) or a software reset (either by setting the gres bit of the hctrl register or because the watchdog timer timed out). alarm1: asserted when the value in the alarm1 register equals the value in the clock register. the interrupt is cleared in one of two ways: * by writing the alarm1 register to a value different than the current value of the clock register. * by testing gpi_13. there is a second method for asserting the alarm1 interrupt and that is by pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 246 setting the gpo line assert_alarm1 (see gpo description for additional details). rx_frame: this is one of two possible receive frame interrupts. the interrupt is asserted after a frame has been received on the mii interface, been written out to packetbuffers in local memory by the dma, the hash search on the mac source and mac destination addresses has been completed, and the frame did not assert one of the gpi lines corresponding to: * rx_ctrl_frame * rx_fifo_ovrun * rxlong * rxshort * rx_crc_err * rx_misalign dma functional block asserts this interrupt. flip thaw_rxlink clears the interrupt. rx_err_frame: this is the second possible receive frame interrupt. the interrupt is asserted after a frame has been received on the mii interface, been written out to packetbuffers in local memory by the dma (if applicable), and the frame asserted one of the gpi lines corresponding to: rx_ctrl_frame rx_fifo_ovrun rxlong rxshort rx_crc_err rx_misalign if a sufficient number of bytes were received to include the mac source and/or destination address then the assertion of this interrupt is held off until the hash search is done on these addresses. dma functional block asserts this interrupt. flip thaw_rxlink clears the interrupt. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 247 tx_done: asserted when a frame is done being transmitted on the link media without collision. this interrupt is conditional on the en_tx_done_inr bit being set (1) in the txf_csr control register. flip thaw_txdone clears the interrupt. collision: asserted by the link transmit interface when a collision is sensed on the mac link interface (that is, the mii col signal became asserted while a frame was being transmit by the pm3351). this interrupt will only be asserted if the link is configured for half-duplex operation. this interrupt becomes asserted when the collision jam sequence begins on the mac link interface. flip thaw_collision clears the interrupt. txf_stop: asserted by the tx_fifo functional block when the frame at the head of the tx_fifo data ram has a disposition code corresponding to stop. this interrupt is cleared when the disposition code in the dshead control register is written by the switch processor to have a disposition code corresponding either to transmit or drop. rpcim_done: the rpcim functional block asserts this interrupt whenever a transaction has completed. flip clr_rpcim_done clears the interrupt. dpi_done: asserted by the dpi functional block (dma transmit channel) to indicate that a data descriptor and its associated linked-list of packetbuffers has been read across the pci expansion bus and the frame data has been written to the tx_fifo data ram. assertion of this interrupt is conditional on having dpi_done_en bit in dpi_ctrl register being set (1). flip thaw_dpi_done clears the interrupt. dpi_hd_done: asserted by the dpi functional block (dma transmit channel) to indicate that the head of a frame has been read across the pci expansion bus. the head refers to the data descriptor and the mac destination and source address that is in the first packetbuffer of the frame. when this interrupt is asserted is conditional on the setting of the learn bit pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 248 of the data descriptor flags field: if learn bit is clear (0), then the interrupt is asserted when the last byte of the source address is read from the pci_biu and is simultaneously written out to the tx_fifo data ram and the hash source address register (hdpisrc). if the learn bit is set (1), then the interrupt is asserted after the hash search is completed on the mac source address hdpisrc. flip thaw_dpi_hd clears the interrupt. ack_int: asserted whenever one of the acknowledge counters on the device is non- zero and the disable_ack_int of the ctrsel register is clear (0). flist_err: asserted by the dma under the following conditions: the flist_lock state bit is clear (0) indicating that the switch processor is not accessing the free list either of these conditions occurs: the dmnfree control register pair has a value of 0 Cor- the dmnfree register pair has the same value as the dmflist register pair. after system initialization by the switch processor the flist_err interrupt should not become asserted. this interrupt condition will be treated by firmware as a fatal and unrecoverable error in the free pool list of packetbuffers. the flist_err interrupt will not be asserted if the free pool of packetbuffers becomes empty. this condition, which occurs when dmflist becomes equal to 0 (but dmnfree is non-zero), can be tested by using the flist_null coprocessor test condition bit. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 249 req_int: asserted whenever one of the request counters on the device is non-zero and all of the following are true: * the gpo line req_lock is clear (0) * the disable_req_int bit in the ctrsel register is clear (0) * the 9-bit hold-off counter (hricntr) is non-zero. the request interrupt is made conditional on req_lock, disable_req_int, and hricntr to allow for possible firmware control in determining the rate at which the request interrupt will occur. the hricntr hold-off counter defaults to 0. it is loaded to a value of 511 when the flip holdoff_req_int occurs. after being loaded, the counter will decrement every sysclk cycle until reaching 0. mintr: this interrupt is asserted whenever the mintr_ pin is logically asserted (that is, has a ttl low logic level). task_intr: this interrupt is asserted whenever the taskctr control register is non-zero. alarm2: this interrupt is asserted when the value in the alarm2 register equals the value in the clock register. the interrupt is cleared in one of two ways: * by writing the alarm1 register to a value different than the current value of the clock register. * by testing gpi_14. there is a second method for asserting the alarm2 interrupt and that is by setting the gpo line assert_alarm2 (see gpo description for additional details). gpi (switch processor general purpose inputs) the switch processor has fifteen gpi lines that are used to read status provided by the various functional blocks on the pm3351 using the test , mtest, or mtestb instructions or by reading the incb special purpose register. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 250 gpi table: hw name description receive error tests: used inside the receive frame error interrupt routine to determine what sort of error occurred. the software uses this information to update the appropriate error counters and dispose of the frame and its associated linked-list of packetbuffers. gpi0: rx_misalign set (1) if received frame is mis-aligned. gpi1: rx_crc_err set (1) if received frame has a crc error (technically, that the 32-bit framechecksequence field of the received frame did not comply with the 802.3 specification). gpi2: rxshort set (1) if the received frame has a size less than the value of the min_size link control register. gpi3: rxlong set (1) if the received frame has a size greater than the value of the max_size link control register. gpi4: rx_fifo_ovrun set (1) if during reception of the present frame either of the two fifos that are part of the link receive functional block experienced an over-run condition. this will cause some of the data in the frame to be lost or corrupted. the rx_crc_err status line will also be set if this error condition occurs. gpi5: rx_ctrl_frame set (1) if the received frame had an ethernet length/type field (the two bytes, in an 802.3 compliant frame, after the source address) equal in value to the etype link control register. request pending test: gpi6: req_present this gpi is essentially the same as the request interrupt. it tests positive if any of the request counters is non-zero. hash lookup tests: used inside the receive frame and the transmit interrupts to determine the state of the hash functional block. gpi7: dmadstfail set (1) if the hash search on the link receive frame destination address failed gpi8: dmasrcfail set (1) if the hash search on the link receive frame source address failed gpi9: dpisrcfail set (1) if the hash search on the source address of the frame read across pci expansion bus (by the dpi functional block) failed gpi10: dmadstbsy hash busy: hash search on link receive destination address has not completed gpi11: dmasrcbsy hash busy: hash search on link receive source address has not completed gpi12: dpisrcbsy hash busy: hash search on source address of frame read across the pci expansion bus alarm tests: used in alarm polling to determine if an alarm triggered. gpi13: alarm 1 triggered. side effect: when tested will de-assert the alarm1 interrupt if presently set. gpi14: alarm 2 triggered pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 251 side effect: when tested will de-assert the alarm2 interrupt if presently set. gpo (switch processor general purpose outputs) the switch processor has thirty-two gpo lines that can be toggled by the use of the flip instruction. these outputs allow firmware to control various functional blocks on the pm3351. the hardware implementation of each gpo line can be either level- sensitive or pulsed for a single cycle. in either case the same switch processor flip instruction is used and whether the signal is used in the internal functional block as level-sensitive or edge-sensitive is a hardware implementation detail that does not concern the programmer. as previously noted, the present status of any of the gpo lines is visible to the switch processor by reading the outcbl and outcbh special purpose registers (which map, respectively, to the gpo[15:0] and gpo[31:16] lines). gpo table: hw name level/ pulse description freelist lock controls: used to allow the switch processor and dma hardware to have shared access to the dmflist and dmnfree control registers. the switch processor is only allowed to modify the contents of the dmflist and dmnfree registers if the internal flist_lock signal is set (1). gpo0 flist_unlock pulse free list lock off. a flip on this gpo line will unconditionally cause the internal flist_lock signal to become clear (0). gpo1 flist_set_lock pulse free list lock on. a flip on this gpo line will unconditionally cause the internal flist_lock signal to become set (1). hash : control line for testing of hash functional block by firmware. gpo2 risc_hash level when set (1), allows the switch processor to initiate a hash search using writes to the hdpisrc, hdmadst, or hdmasrc control registers. set only for testing purposes. request and acknowledge counters: gpo3 risc_req_lock level used to qualify the req_int interrupt. when set (1), the req_int interrupt will not be asserted. as a side note, the interrupt mask registers (emask, esch) can be used to perform the same function. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 252 gpo4 req_dec pulse a flip causes one of the eight request counters to decrement. decrements the selected request counter (see reqid_num field of the reqid control register). the counters get selected and prioritized by the counter functional block. gpo5 ack_dec pulse a flip causes one of the eight acknowledge counters to decrement. decrements the selected acknowledge counter (see ackid_num field of ctrsel register). the counters get selected and prioritized by the counter functional block. gpo6 task_inc pulse a flip causes the taskctr control register to increment. gpo7 task_dec pulse a flip causes the taskctr control register to decrement. gpo8 test_cntr_incr pulse used for factory testing only. gpo9 holdoff_req_int pulse a flip causes the req_int interrupt to be unconditionally de-asserted for the next 512 sysclk cycles. gpo10 fdplx_txpause level when set (1), inhibits reading of data frames from the tx_fifo data ram. this gpo line is used by the switch processor, in conjunction with a software timer, to implement the pause operation as per 802.3x, clause 31. gpo11 - level unused gpo12 - level unused gpo13 - level unused thaw flips: this group of gpo lines is used to implement flow control between the various functional blocks and the firmware. gpo14 thaw_flist_int pulse this flip will clear (0) the flist_err interrupt line. however, if the condition which caused the flist_err interrupt in the first place is still true, then the interrupt will remain asserted. gpo15 thaw_rxlnk pulse this flip will clear (0) the receive frame interrupt condition (either rx_frame or rx_err_frame) and permits the dma functional block to start reading the next frame from the link receive functional block. as previously noted, the logical implementation of the dma and link receivechannel is such that the dma module can hold the status of the previously received frame while the current frame is being received. consider a receive frame sequence of: frame #n, #n+1, #n+2 a link receive fifo over-run condition will not occur unless the servicing of the dma interrupt for frame #n has not been cleared via a flip on thaw_rxlnk before the first 64 data bytes of frame #n+1 have been impressed on the mii receive interface pins. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 253 gpo16 thaw_collision pulse this flip will clear (0) the collision interrupt line and: (1) the txlatecol transmit status bit is cleared (2) it allows the tx_fifo output state machine to leave a collision holding state, thereby allowing either another attempt at transmitting the frame or for the frame to be dropped (see dshead control register description). gpo17 thaw_dpi_done pulse this flip will clear the dpi_done interrupt line, thereby allowing the dpi state machine to transition to idle. this allows the next frame to be fetched by reading across the pci expansion bus. gpo18 thaw_txdone pulse this flip will clear the tx_done interrupt line and allows the next transmit frame status to be loaded into the txf_dsize control register. as previously noted, the logical implementation of the tx_fifo and link transmit channel is such that the tx_fifo module can hold the status of the previously transmitted frame while transmitting the current frame. consider a transmit frame sequence of: frame #n, #n+1, #n+2 assume that there are no collisions on the link. the tx_fifo will not enter a flow control state having to do with the servicing of the tx_done interrupt for frame #n+1 unless the tx_done interrupt corresponding to frame #n has not been cleared via a flip on thaw_txdone by the time that the last data byte of frame #n+1 has been transmit on the mii transmit interface pins. gpo19 thaw_dpi_hd pulse this flip will clear the dpi_hd_done interrupt line. the dpi state machine will not return to idle after completing the read of the presently fetched frame across the pci expansion bus unless the dpi_hd_done interrupt is clear. gpo20 clr_rpcim_done pulse this flip will clear the rpcim_done interrupt line. this allows the rpcim state machine to return to idle and start the next pci transaction. gpo21 gpo_txfi_rwfra me level asserted while the switch processor is writing a frame into either the tx_fifo data ram or mac ctrl ram. the first flip (leading edge assertion of gpo_txfi_rwframe) is interpreted as the beginningofframe. the second flip (de-assertion of gpo_txfi_rwframe) is interpreted as the endofframe and results in the completion of the frame write into the target fifo. the switch processor writes the frame data as previously discussed in the section dealing with the tx_fifo control registers. enable flips: these flips are used to trigger hardware procedures. gpo22 go_req pulse this flip will initiate the transfer handshake channel to do a request counter increment pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 254 gpo23 go_ack pulse this flip will initiate the transfer handshake channel to do an acknowledge counter increment gpo24 go_dpi pulse this flip sets a valid status bit in the dpi functional block (dma transfer channel) that indicates that the data descriptor pointer in the remdd is to be read across the pci expansion bus. gpo25 go_txmcframe pulse this flip sets a valid status bit in the tx_fifo module that indicates that a mac control frame should be transmit (the implicit assumption is that the switch processor will have written the correct frame contents to the mac control frame ram prior to doing the go_txmcframe flip). mdio outputs: these flips are used to control the mii management interface pins: mdc and mdio. gpo26 o_mdc level the level of this gpo line corresponds to the ttl logic level on the mdc pin. gpo27 o_mdio level the level of this gpo line corresponds to the ttl logic level driven by the pm3351 on the mdio pin if the output enable, oe_mdio, is set (1). gpo28 oe_mdio level mdio output enable. if set (1) then the mdio tristate output buffer is enabled and the mdio pin is driven to the value of the o_mdio gpo line. switch processor testing flips: these flips are used for test purposes. gpo29 rint level rint is a mask-able interrupt source for the int_ pin on the pm3351. if gpo29 is set (1) and the rintmsk bit is set in hctrl, then the int_ pin will be asserted (a ttl logic low). see description of rint in host interface status (hstat) and control (hctrl) registers for additional details. gpo30 assert_alarm1 level if set (1), the alarm1 interrupt line will be asserted. gpo31 assert_alarm2 level if set (1), the alarm2 interrupt line will be asserted. coprocessor test conditions the switch processor has 16 coprocessor conditions. from a programmers standpoint they are not much different than the gpi inputs except that they are tested by using different instructions (bcop and bncop). coprocessor # hw name description cop0: link_idle set (1) if both the link transmit and receive channels are idle. this test condition is not required for switching applications and is mapped to a cop_condition bit for observability. cop1: any_rxframe_int set (1) if either link receive interrupt line is set. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 255 cop2: rx_frame this coprocessor test condition line is mapped to the rx_frame interrupt line. the combination of cop1 and cop2 allows an efficient means (branch-and-test ) for the switch processor to test for an outstanding receive frame interrupt while it is servicing a lower priority, but possible lengthy, interrupt service routine. cop3: dpo_idle transfer handshake channel (i.e. dpo functional block) is in idle state. the transfer handshake channel is in the idle state if there are no outstanding increment request counter or increment acknowledge counter operations. the switch processor should test for this bit being set (1) before writing to the template dd registers in the transfer handshake channel. cop4: fdplx this line is logically the same as the lnctrl register fdplx bit (set to 1 if the link is configured for full duplex). cop5: rpcim_idle set (1) if the rpcim module is in an idle state. cop6: i_mdio_r this coprocessor condition bit is mapped to the mdio input buffer. it is tested during mii management reads to determine if the mdio pin being driving by the external phy device is a 0 or a 1. cop7: any_dpo_af set (1) if any of the eight transfer rings are full or almost- full (that is, within 1 element of being full). cop8: flist_null set (1) if the dmflist control register pair is equal to 0. cop9: txf_af set (1) if the tx_fifo data ram is almost full. the almost full condition is set when the data ram has less free space than that corresponding to the pbsize control register. txf_af is tested by the switch processor during the write of frame data into the tx_fifo data ram. cop10: dpi_txfi_idle entire pci frame read expansion port is in idle state up to the logical tail of the tx_fifo. this coprocessor condition is expected to be used for testing before firmware starts to write a transmit management frame (that is a frame created by the switch processor) to the tx_fifo data ram. cop11: txfo_idle tx_fifo ostate state machine is idle cop12: txfomc_idle tx_fifo omcstate state machine is idle cop13: txmcframe_empty tx_fifo mac control frame data ram is empty cop14: cop_regs[0] this is mapped to the cop_regs[0] bit in the dmctrl register. implemented to allow software set-able branch- test condition. cop15: cop_regs[1] this is mapped to the cop_regs[1] bit in the dmctrl register. implemented to allow software set-able branch- test condition. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 256 operation power supply sequencing due to esd protection structures in the pads it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions it is possible to blow these esd protection devices or trigger latch up. the recommended power supply sequencing follows: 1. vbias power must be supplied either before vddi and vddo or simultaneously with vddi and vddo to prevent current flow through the esd protection devices which exist between vbias and vddi/vddo power supplies. 2. vddi power must be supplied either before vddo or simultaneously with vddo to prevent current flow through the esd protection devices which exist between vddi and vddo power supplies. connection to a common vdd power plane is the recommended standard practice for customer applications. 3. to prevent damage to the esd protection on the device inputs the maximum dc input current specification must be respected. this is accomplished by either ensuring that the vddi power is applied before input pins are driven or by increasing the source impedance of the driver so that the maximum driver short circuit current is less than the maximum dc input current specification (20 ma). 4. power down the device in the reverse sequence. pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 257 mechanical information 1 a a2 d d1 e e1 208 e 8-12 deg. pin 1 designator a1 .25 2) dimensions shown are nominal with tolerances as indicated. 3) foot length "l" is measured at notes: 1) all dimensions in millimeter. gage plane, 0.25 above seating plane. 0-7 deg detail a a c 0-10 deg. b standoff lead coplanarity c seating plane c ccc l 0.13-0.23 see detail a 8-12 deg. 0.27 0.17 28 x 28 x 3.49 mm package type: max. nom. 4.07 min. dim. 3.64 a body size: 208 pin metric plastic quad flatpack-mqfp 0.48 3.59 3.49 30.80 30.60 28.10 28.00 0.25 a1 3.39 a2 30.40 d 27.90 d1 30.80 30.60 28.10 28.00 0.75 0.60 0.50 30.40 e 27.90 e1 0.50 l e 0.10 ccc b 0.22 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 258 pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 259 ordering and thermal information part no. description pm3351-rc 208 plastic quad flat pack (pqfp) PM3351-SW switching code firmware part no. case temperature theta ja pm3351-rc -0c to 70c 28 c/w pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 260 notes pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch proprietary and confidential to pmc-sierra, inc., and for its customers internal use 261 notes pm3351 elan 1x100 data sheet pmc-970113 issue 3 single port fast ethernet switch none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pm-970113 (r3) ref pmc-961052 (r3) issue date: february 1998 proprietary and confidential to pmc-sierra, inc., and for its customers internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com |
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